公开(公告)号：EP2701196A3

公开(公告)日：2017-04-26

申请号：EP13179637.7

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Khare, Prasanna ,  Loubet, Nicolas

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract translation: 一种半导体器件包括其中具有沟道区的半导体衬底，在沟道区上方的栅极结构以及在栅极结构的相对侧上的源极区和漏极区。 各个触点位于每个源极和漏极区域上。 源区和漏区中的至少一个具有与相应触点倾斜的上接触表面。 倾斜的上接触表面比相应的平坦接触表面具有至少大50％的面积。

公开(公告)号：EP2743976A1

公开(公告)日：2014-06-18

申请号：EP13196969.3

申请日：2013-12-12

Applicant: STmicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Fenouillet-Beranger, Claire ,  Denorme, Stéphane ,  Loubet, Nicolas ,  Liu, Qing ,  Richard, Emmanuel ,  Perreau, Pierre

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: L'invention concerne un procédé de fabrication d'un substrat hybride SOI/massif, comprenant les étapes suivantes :
a) partir d'une plaquette SOI comprenant une couche semiconductrice monocristalline appelée couche SOI (3), sur une couche isolante (2), sur un substrat semiconducteur monocristallin (1) ;
b) déposer sur la couche SOI au moins une couche de masquage (17, 18) et former des ouvertures traversant la couche de masquage, la couche SOI et la couche isolante jusqu'à atteindre le substrat ;
c) faire croître par une alternance répétée d'étapes d'épitaxie sélective et de gravure partielle un matériau semiconducteur (27) ; et
d) graver des tranchées d'isolement entourant lesdites ouvertures remplies de matériau semiconducteur, en empiétant vers l'intérieur sur la périphérie des ouvertures.

Abstract translation: 该方法包括在绝缘体上半导体（SOI）层（3）上沉积掩模层（17,18），以及形成穿过掩模层，SOI层和绝缘层（2）的开口， 晶体半导体衬底（1）。 通过选择性外延和部分蚀刻步骤的重复交替，半导体材料生长到期望的最终水平，而不形成间隔物。 围绕填充有半导体材料的开口的绝缘沟槽（30）被蚀刻，同时在开口的周边上向内侵入。

公开(公告)号：EP2738814A1

公开(公告)日：2014-06-04

申请号：EP13194927.3

申请日：2013-11-28

Applicant: STMicroelectronics, Inc.

Inventor： Loubet, Nicolas ,  Khare, Prasanna

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/785

Abstract: Despite improvements in FinFETs and strained silicon devices, transistors continue to suffer performance degradation as device dimensions shrink. These include, in particular, leakage of charge between the semiconducting channel and the substrate. An isolated channel FinFET device prevents channel-to-substrate leakage by inserting an insulating layer between the channel (fin) and the substrate. The insulating layer isolates the fin from the substrate both physically and electrically. To form the isolated FinFET device, an array of bi-layer fins can be grown epitaxially from the silicon surface, between nitride columns that provide localized insulation between adjacent fins. Then, the lower fin layer can be removed, while leaving the upper fin layer, thus yielding an interdigitated array of nitride columns and semiconducting fins suspended above the silicon surface. A resulting gap underneath the upper fin layer can then be filled in with oxide to isolate the array of fin channels from the substrate.

Abstract translation: 尽管FinFET和应变硅器件有所改进，晶体管在器件尺寸缩小的同时仍继续遭受性能的降低。 这些特别包括在半导体沟道和衬底之间的电荷泄漏。 隔离沟道FinFET器件通过在沟道（鳍）和衬底之间插入绝缘层来防止沟道对衬底的泄漏。 绝缘层物理和电气都将散热片与基板隔离开来。 为了形成隔离的FinFET器件，可以从硅表面，在提供相邻鳍片之间的局部绝缘的氮化物柱之间外延生长双层鳍片阵列。 然后，可以除去下部翅片层，同时留下上部翅片层，从而产生悬挂在硅表面上方的氮化物柱和半导体翅片的交错排列。 然后可以用氧化物填充在上鳍片下方的所得间隙，以将翅片通道阵列与基底隔离。

公开(公告)号：EP2701187A3

公开(公告)日：2014-04-23

申请号：EP13179641.9

申请日：2013-08-07

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Liu, Qing ,  Loubet, Nicolas ,  Khare, Prasanna ,  Ponoth, Shom ,  Vinet, Maud ,  Doris, Bruce

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L29/66772 ,  H01L29/78654

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overflying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion af the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

公开(公告)号：EP2701196A2

公开(公告)日：2014-02-26

申请号：EP13179637.7

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Khare, Prasanna ,  Loubet, Nicolas

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/76816 ,  H01L21/823425 ,  H01L21/823864 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.

Abstract translation: 半导体器件包括其中具有沟道区域的半导体衬底，沟道区域上方的栅极结构以及栅极结构的相对侧上的源极和漏极区域。 每个源极和漏极区域上都有一个相应的触点。 源极和漏极区域中的至少一个具有与相应触点的倾斜的上部接触表面。 倾斜的上接触表面具有比相应的平坦接触表面至少大50％的面积。

公开(公告)号：EP2701197A1

公开(公告)日：2014-02-26

申请号：EP13179638.5

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Khare, Prasanna ,  Loubet, Nicolas

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/0886 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

Abstract translation: 阿多鳍片FinFET器件可以包括基底和半导体鳍从衬底向上延伸的多个部分并加以沿着基板间隔开。 每个半导体鳍可以具有相对的第一和第二端之间的中间部分那里，半导体鳍的多个最外翼片可包括在其外表面上外延生长的屏障。 所述鳍式场效应晶体管还可以包括至少一个栅极覆盖所述半导体鳍片的中间部分，所述半导体鳍片邻近第一端部之间提出的外延半导体源极区的多个，并且提出了外延半导体漏区的半导体鳍片邻近之间的多个 第二其两端。

公开(公告)号：EP2701187A2

公开(公告)日：2014-02-26

申请号：EP13179641.9

申请日：2013-08-07

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Liu, Qing ,  Loubet, Nicolas ,  Khare, Prasanna ,  Ponoth, Shom ,  Vinet, Maud ,  Doris, Bruce

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L29/66772 ,  H01L29/78654

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overflying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion af the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract translation: 一种电子设备可以包括一个基底，一个隐埋氧化物（BOX）层，覆盖所述基材，所述至少一个半导体器件飞越BOX层，并在基板的至少一个浅沟槽隔离（STI）区域和邻近所述至少一个半导体 装置。 所述至少一个STI区限定的侧壁表面与所述底物和可以包括在氧化物层衬底部分Af的侧壁面，氮化物层衬底部上方的侧壁面的顶部，并在内的绝缘材料 氮化物和氧化物层。

公开(公告)号：EP2701187B1

公开(公告)日：2016-10-26

申请号：EP13179641.9

申请日：2013-08-07

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Liu, Qing ,  Loubet, Nicolas ,  Khare, Prasanna ,  Ponoth, Shom ,  Vinet, Maud ,  Doris, Bruce

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L29/66772 ,  H01L29/78654

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overflying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion af the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

公开(公告)号：EP2720259A2

公开(公告)日：2014-04-16

申请号：EP13187223.6

申请日：2013-10-03

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Loubet, Nicolas ,  Liu, Qing ,  Ponoth, Shom

IPC: H01L21/84 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/31111 ,  H01L21/76232 ,  H01L21/84

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

Abstract translation: 通过将衬底上的掩埋氧化物覆盖在衬底中以及通过有源硅层上的任何焊盘电介质的有源硅层蚀刻绝缘沟槽。 有源硅层的横向外延生长在隔离沟槽中形成突起到至少约5纳米的横向距离，并且围绕突起的部分隔离沟槽被电介质填充。 在包括电介质的有源硅层的部分上形成凸起的源/漏区。 结果，穿过凸起的源极/漏极区域的边缘的不对准触点在隔离沟槽中保持与衬底的侧壁间隔开。

公开(公告)号：EP2701186A1

公开(公告)日：2014-02-26

申请号：EP13179640.1

申请日：2013-08-07

Applicant: STMicroelectronics, Inc.

Inventor： Liu, Qing ,  Loubet, Nicolas ,  Khare, Prasanna

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L21/76264

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract translation: 一种电子设备可以包括一个基底，一个隐埋氧化物（BOX）层，覆盖所述基材，所述至少一个半导体器件上覆于BOX层，和至少一个STI区域中的基底和邻近至少一个半导体器件。 所述至少一个STI区定义了与基板的侧壁表面，并且可以包括氮化物层衬在侧壁表面的氧化层衬底部上方的侧壁面的顶部部分的底部部分，和在内部的绝缘材料 氮化物和氧化物层。