公开(公告)号：EP1271478A3

公开(公告)日：2006-12-06

申请号：EP02253867.2

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B5/596 ,  G11B5/55

CPC classification number: G11B5/59633

Abstract: A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

公开(公告)号：EP1271507A3

公开(公告)日：2003-10-22

申请号：EP02253883.9

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B19/20 ,  G11B19/28 ,  G11B5/596

CPC classification number: G11B5/59633 ,  G11B19/20 ,  G11B19/28

Abstract: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. On spin up of the disk, the processor detects a spin-up wedge associated with one of the servo wedges and then detects the servo wedge. Once the servo wedge is detected, a head-position circuit can read the location data from the servo wedge to determine an initial position of the read-write head. By detecting a both a spin-up wedge and a servo wedge to determine an initial head position on disk spin up, such a servo circuit often allows one to increase the disk's storage capacity by reducing the lengths of the spin-up wedges.

公开(公告)号：EP1126617A2

公开(公告)日：2001-08-22

申请号：EP01300806.5

申请日：2001-01-30

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: H03L7/091 ,  G11B20/14 ,  G11B20/10

CPC classification number: H04L7/0054 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10296 ,  G11B20/1403 ,  H03L7/091 ,  H04L7/0029 ,  H04L2007/047

Abstract: A phase-calculation circuit (46) includes a buffer (42), an approximation circuit (70), and an interpolator (56). The buffer receives and stores first and second samples of a periodic signal having a peak amplitude. The approximation circuit (70) linearly approximates a portion of the periodic signal, and calculates the relative phase of one of the samples within the signal portion. The interpolator (56) calculates the absolute phase of that sample with respect to a predetermined point of the signal using the relative phase and the values of the first and second samples. The circuit is used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the preamble and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery circuit uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock and reduces the overall alignment-acquisition time.

Abstract translation: 一种相计算电路（46）包括一个缓冲器（42），上近似电路（70），并在内插器（56）。 缓冲器接收并存储具有峰值振幅的周期信号的第一和第二样品。 近似电路（70）线性地近似于周期性信号的一部分，并计算信号部分内的样本中的一个的相对相位。 内插器（56）计算样本的绝对相位相对于使用的相对相位和所述第一和第二样本的值的信号的一个预定点一样。 该电路用于降低数字定时恢复环的对准捕获时间，并允许该前同步码的缩短和在磁盘的数据存储密度也相应增加。 该电路可以在一个磁盘驱动器的读出信号和一个读出信号采样时钟之间的初始相位差确定性矿。 数字定时恢复电路使用该相位差，以提供初始的读出信号和采样时钟之间的粗略对准和降低了整体对准捕获时间。

公开(公告)号：EP1271506B1

公开(公告)日：2013-04-24

申请号：EP02253882.1

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B19/20 ,  G11B19/28 ,  G11B5/596

CPC classification number: G11B5/59633 ,  G11B19/20 ,  G11B19/28

公开(公告)号：EP1271512A3

公开(公告)日：2007-08-22

申请号：EP02253868.0

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B20/10 ,  G11B20/12 ,  G11B20/18 ,  H04L1/00 ,  H03M13/41

CPC classification number: H03M7/16 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10175 ,  G11B20/10222 ,  G11B20/10296 ,  G11B20/1403 ,  G11B20/18 ,  G11B2020/1282 ,  G11B2020/1284 ,  G11B2020/1484 ,  G11B2020/1859 ,  G11B2020/1863 ,  H03M13/41 ,  H03M13/6343

Abstract: A viterby-detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

公开(公告)号：EP1271480A3

公开(公告)日：2006-12-06

申请号：EP02253885.4

申请日：2002-05-31

Applicant: STMicroelectronics, Inc.

Inventor： Heydari, Fereidoon ,  Ozdemir, Hakan

IPC: G11B5/596

CPC classification number: G11B5/59655 ,  G11B5/59688

Abstract: A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation ― called burst integration ― typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

公开(公告)号：EP1126616A2

公开(公告)日：2001-08-22

申请号：EP01300785.1

申请日：2001-01-30

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan ,  Byrne, Jason D.

IPC: H03L7/091 ,  G11B20/14 ,  G11B20/10

CPC classification number: G11B20/10037 ,  G11B20/10009 ,  G11B20/1403 ,  H03L7/091

Abstract: A circuit includes a buffer (42) for receiving and storing two samples of a signal, and a phase calculation circuit (46) for calculating a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing such coarse alignment, the recovery loop reduces the overall alignment-acquisition time.

Abstract translation: 一种电路包括：用于接收和存储一个信号的两个样品用于计算样品中的一个和信号的预定点之间的相位差的缓冲器（42），和一个相位计算电路（46）。 这样的电路可被用于降低数字定时恢复环的对准捕获时间，并允许该扇区的前同步码的缩短，并在盘的数据存储密度也相应增加。 该电路可以在一个磁盘驱动器的读出信号和一个读出信号采样时钟之间的初始相位差确定性矿。 数字定时恢复环路使用该相位差，以提供初始的读出信号和采样时钟之间的粗略对准。 通过提供搜索粗对准，回收循环降低了整体的定位采集时间。

公开(公告)号：EP1126457A2

公开(公告)日：2001-08-22

申请号：EP01300805.7

申请日：2001-01-30

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B20/10 ,  G11B5/09

CPC classification number: G11B20/10055 ,  G11B5/012 ,  G11B20/10009 ,  G11B20/10027 ,  G11B20/10037 ,  G11B20/1403

Abstract: An amplifier gain control includes a buffer that stores two samples of an amplified information signal, and a coupled gain-determination circuit. The gain-determination circuit generates a gain adjustment based on the two samples and causes the amplifier to shift the amplitude of the amplified information signal toward a predetermined amplitude. This provides an initial, coarse gain adjustment to a read-signal amplifier in a disk-drive read channel. This initial adjustment promotes faster settling of the amplifier gain at the beginning of a data sector and allows the data sector to have a shorter preamble, and the disk to have a higher data-storage density. As the phase angle between the sample clock and the preamble sinusoid may be unknown at the beginning of the data sector, the circuit can determine the initial gain adjustment independent of this phase angle.

Abstract translation: 放大器增益控制包括存储放大信息信号的两个样本的缓冲器和耦合增益确定电路。 增益确定电路基于两个采样产生增益调整，并使放大器将放大的信息信号的幅度向预定的幅度移动。 这为磁盘驱动器读通道中的读信号放大器提供初始的粗增益调整。 该初始调整促进了在数据扇区开始处的放大器增益的更快的建立，并允许数据扇区具有较短的前导码，并且该盘具有更高的数据存储密度。 由于采样时钟和前导码正弦曲线之间的相位角在数据扇区的开头可能是未知的，所以电路可以独立于该相位角确定初始增益调整。

公开(公告)号：EP1089486B1

公开(公告)日：2006-11-29

申请号：EP00308180.9

申请日：2000-09-20

Applicant: STMicroelectronics, Inc.

Inventor： Rezzi, Francesco ,  Ozdemir, Hakan

IPC: H04L7/04 ,  G11B20/16 ,  H03M13/31

CPC classification number: H03M13/6343 ,  G11B20/16 ,  H03M13/41 ,  H03M13/4107 ,  H03M13/6502 ,  H04L7/041 ,  H04L7/042 ,  H04L7/046

公开(公告)号：EP1713070A1

公开(公告)日：2006-10-18

申请号：EP06252039.0

申请日：2006-04-12

Applicant: STMicroelectronics, Inc.

Inventor： Ozdemir, Hakan

IPC: G11B20/10 ,  G11B20/14

CPC classification number: G11B5/09 ,  G11B20/10009

Abstract: A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel. The gain controller may also allow the GA loop and the GT loop to be completely contained with in the digital portion of the read channel.

Abstract translation: 对于读信道的增益环路增益控制器包括一个比较器电路到累加器电路和功能电路。 比较器电路bestimmt的读信号的实际样品和读取信号中的对应的理想的样品，和累加器电路之间的误差保持在响应于该误差的增益校正值和bestimmt增益校正值。 功能电路基因速率通过执行数学预定操作涉及的增益校正值，并提供增益校正信号，以一个可变增益放大器的增益校正信号所做的是可操作以放大的读出信号的实际采样。 因为寻求一个增益控制器允许一个定位在读通道中的模拟数字转换器（ADC）后的可变增益放大器（VGA），增益控制器可以显着地降低增益获取的等待时间（GA）环 或读通道的增益跟踪（GT）循环。 因此，该增益控制器可以允许GA环和GT环路被完全呼叫在读通道的数字部分载带。