Power limiting time delay circuit
    2.
    发明公开
    Power limiting time delay circuit 有权
    功率限制延时电路

    公开(公告)号:EP1383033A3

    公开(公告)日:2007-11-14

    申请号:EP03253400.0

    申请日:2003-05-30

    Inventor: Wenzel, Edward

    CPC classification number: G06F1/28 G05F1/569 G06F1/26 Y10T307/944

    Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

    Power limiting time delay circuit
    3.
    发明公开
    Power limiting time delay circuit 有权
    Leistungsbegrenzungszeitverzögerungsschaltung

    公开(公告)号:EP1383033A2

    公开(公告)日:2004-01-21

    申请号:EP03253400.0

    申请日:2003-05-30

    Inventor: Wenzel, Edward

    CPC classification number: G06F1/28 G05F1/569 G06F1/26 Y10T307/944

    Abstract: A power limiting circuit for power supply that is controlled by a power supply control module includes a shunt regulator having a reference input operatively connected to a voltage input that receives a voltage representative of the power supply control module connected thereto. The shunt regulator is biased on when the voltage at the reference input increases above a reference voltage established at the voltage input. A transistor is operatively connected to the shunt regulator and to an output operatively connected to the power supply control module and has a voltage that is representative of voltage operating the power supply control module. The transistor is biased on from the shunt regulator such that the shunt regulator and transistor form a latch when the voltage at the output reduces below an off voltage level to turn off the power supply, dropping the input voltage, and restarting the power supply in a restart cycle.

    Abstract translation: 由电源控制模块控制的用于电源的功率限制电路包括具有可操作地连接到电压输入的参考输入的并联调节器,该电压输入接收代表与其连接的电源控制模块的电压。 当参考输入端的电压增加到电压输入端所建立的参考电压时,分流稳压器被偏置。 晶体管可操作地连接到分流调节器和可操作地连接到电源控制模块的输出端,并且具有代表操作电源控制模块的电压的电压。 晶体管从分流调节器偏置,使得当输出端的电压降低到关断电压以下时,并联调节器和晶体管形成锁存器,以关闭电源,降低输入电压,并重新启动电源 重启循环。

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