公开(公告)号：EP1367493A1

公开(公告)日：2003-12-03

申请号：EP02253819.3

申请日：2002-05-30

Applicant: STMicroelectronics, Ltd.

Inventor： Bailey, Paul

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0215 ,  G06F12/0862 ,  G06F2212/6022

Abstract: A computer system comprising a plurality of data processing elements connected through a shared communication bus to a memory so that for a given computer cycle at least one of the elements assumes control of the bus for accessing address in memory. The computer system having memory access circuitry connected between the data processing elements and memory which has first and second buffer units for storing prefetched bursts of data from the memory. The buffer circuit also having control logic for prefetching data in sequential bursts from the memory and storing the prefetched burst in the first or second buffer units and the control logic monitors the buffer units and the address to be accessed in memory to determine in which buffer the next fetched burst should be stored.

Abstract translation: 一种包括多个数据处理单元的计算机系统，所述多个数据处理单元通过共享通信总线连接到存储器，从而对于给定的计算机周期，至少一个单元承担控制总线以访问存储器中的地址。 该计算机系统具有连接在数据处理单元和存储器之间的存储器访问电路，该存储器具有用于存储来自存储器的预取突发数据的第一和第二缓冲单元。 该缓冲电路还具有控制逻辑，用于从存储器顺序突发地预取数据并将预取的突发存储在第一或第二缓冲单元中，并且控制逻辑监视缓冲单元和要在存储器中访问的地址以确定在哪个缓冲区中 应该保存下一个取得的爆发。