公开(公告)号：EP1347650A1

公开(公告)日：2003-09-24

申请号：EP02251932.6

申请日：2002-03-18

Applicant: STMicroelectronics, Ltd.

Inventor： Bolton, Martin

IPC: H04N7/50

CPC classification number: H04N19/42 ,  H04N19/126 ,  H04N19/13 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172 ,  H04N19/176 ,  H04N19/61 ,  H04N19/91

Abstract: Compression circuitry for generating an encoded bitstream from a plurality of video frames. Data is DCT transformed and then streamed to a processor where quantised and inverse quantised blocks are generated. A second streaming data connection streams the inverse quantised blocks to an inverse DCT block to generate reconstructed prediction error macroblocks. An addition circuit adds each reconstructed prediction error macroblock and its corresponding predictor macroblock to generate a respective reconstructed macroblock. The quantised macroblocks are zig-zag scanned, run level coded and variable length coded to generate an encoded bitstream.

Abstract translation: 用于从多个视频帧生成编码比特流的压缩电路。 数据被DCT变换，然后流式传输到生成量化和反量化块的处理器。 第二流数据连接将逆量化块流向逆DCT块，以产生重建的预测误差宏块。 加法电路将每个重建的预测误差宏块及其对应的预测器宏块相加以生成相应的重建宏块。 经量化的宏块被锯齿扫描，运行电平编码和可变长度编码以生成编码比特流。