公开(公告)号：EP0947995A3

公开(公告)日：2001-11-14

申请号：EP99302536.0

申请日：1999-03-31

Applicant: STMicroelectronics, Ltd.

Inventor： Docker, Steven Charles

IPC: G11C29/00

CPC classification number: G11C29/50

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

公开(公告)号：EP0947995A2

公开(公告)日：1999-10-06

申请号：EP99302536.0

申请日：1999-03-31

Applicant: Stmicroelectronics, Ltd.

Inventor： Docker, Steven Charles

IPC: G11C29/00

CPC classification number: G11C29/50

Abstract: A method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.

Abstract translation: 一种用于测试包括交叉耦合排列的第一和第二晶体管以形成双稳态锁存器的半导体存储器单元的方法，晶体管的漏极分别代表第一和第二节点，每个节点用于存储高电位或低电位状态，并且每个节点被连接 到相应的半导体装置，用于替换从节点泄漏的电荷和可由字线激活的相应开关装置，用于将节点耦合到相应的位线，所述方法包括以下步骤：将位线连接到 低潜力; 激活字线以将第一节点连接到第一位线以允许第一节点上的任何电势下降到第一位线上的电势; 以及监视从第一节点到第一位线的电荷流动以测试第一半导体装置的操作。