公开(公告)号：EP0981080B1

公开(公告)日：2003-09-17

申请号：EP99304339.7

申请日：1999-06-03

Applicant: STMicroelectronics, Ltd.

Inventor： Knowles, Simon

IPC: G06F7/50

CPC classification number: G06F7/508 ,  G06F2207/5063

公开(公告)号：EP0981080A1

公开(公告)日：2000-02-23

申请号：EP99304339.7

申请日：1999-06-03

Applicant: Stmicroelectronics, Ltd.

Inventor： Knowles, Simon

IPC: G06F7/50

CPC classification number: G06F7/508 ,  G06F2207/5063

Abstract: A method of designing an addition circuit, and an addition circuit designed according to the method are described. The design technique is optimised to facilitate design of an addition circuit of minimum depth. The design technique takes into account the number of logical stages of the addition circuit and the manner in which those stages are connected by spanning paths to create fan-out nodes. The number of fan-out nodes per level can be optimised.

Abstract translation: 描述了一种设计加法电路的方法，以及根据该方法设计的加法电路。 优化了设计技术，以便于设计最小深度的加法电路。 设计技术考虑了加法电路的逻辑级数以及通过跨越路径连接这些级的方式来创建扇出节点。 可以优化每个级别的扇出节点数量。