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1.发明公开Circuitry for carrying out square root and division operations 审中-公开Schaltung zurDurchführungvon Quadratwurzel und Divisions operations
公开(公告)号：EP1315080A1
公开(公告)日：2003-05-28
申请号：EP01309851.2
申请日：2001-11-22
Applicant: STMicroelectronics, Ltd.
Inventor： Kurd, Tariq
CPC classification number: G06F7/535 , G06F7/5525
Abstract: The invention provides circuitry for carrying out a square root operation and a division operation. The circuitry comprises common iteration circuitry for carrying out a plurality of iterations and means for identifying if an square root operation or a division operation is to be performed. The iteration circuitry is controlled in accordance with whether a square root or division operation is to be performed.
Abstract translation: 本发明提供了用于执行平方根操作和分割操作的电路。 电路包括用于执行多个迭代的公共迭代电路和用于识别是否要执行平方根操作或除法运算的装置。 根据是否执行平方根或除法运算来控制迭代电路。
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2.发明公开Circuitry for carrying out at least one of a square root operation and a division operation 有权电路用于执行平方根操作的至少一个，并且分
公开(公告)号：EP1315081A1
公开(公告)日：2003-05-28
申请号：EP01309854.6
申请日：2001-11-22
Applicant: STMicroelectronics, Ltd.
Inventor： Kurd, Tariq
CPC classification number: G06F7/535 , G06F7/5525
Abstract: The invention provides circuitry for carrying out at least one of a square root operation and a division operation. The circuitry comprises a carry save adder, and a carry propagate adder part. The carry save adder and the carry propagate adder part are arranged in parallel.
Abstract translation: 本发明提供了用于执行平方根手术中的至少一个和一个除法运算电路。 所述电路包括一个进位保存加法器和进位传送加法器部分。 进位保存加法器和进位加法器繁殖部分平行布置。
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3.发明公开Circuit for calculation of division and square root with floating point numbers 审中-公开Schaltung zum Berechnen von Division und Quadratwurzel mit Gleitkommazahlen
公开(公告)号：EP1315079A1
公开(公告)日：2003-05-28
申请号：EP01309849.6
申请日：2001-11-22
Applicant: STMicroelectronics, Ltd.
Inventor： Kurd, Tariq
CPC classification number: G06F7/535 , G06F7/483 , G06F7/4873 , G06F7/5375 , G06F7/5525 , G06F2207/5528
Abstract: The invention provides circuitry for carrying out an arithmetic operation requiring a plurality of iterations. The circuitry comprises N sets of iteration circuitry arranged one after the other so that at least one of the sets of iteration circuitry receives an output from a preceding one of the sets of iteration circuitry. Each of the sets of iteration circuitry comprises at least one adder part, wherein a full adder is provided by at least one part in one of the sets of iteration circuitry and a second part in a succeeding one of the sets of iteration circuitry.
Abstract translation: 本发明提供用于执行需要多次迭代的算术运算的电路。 该电路包括一组相继布置的N组迭代电路，使得迭代电路组中的至少一个接收来自迭代电路组之前的一组的输出。 迭代电路组中的每一个包括至少一个加法器部分，其中全加器由迭代电路组之一中的至少一个部分提供，并且迭代电路组中的后一组中的第二部分。
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