公开(公告)号：EP1655667A3

公开(公告)日：2008-10-29

申请号：EP05447243.6

申请日：2005-11-04

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph ,  Charlier, Vincent ,  Rahaga, Tiana ,  Vandersmissen, Yves

IPC: G06F12/06

CPC classification number: G06F9/30149 ,  G06F9/322 ,  G06F9/328 ,  G06F12/0638

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialisation process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

公开(公告)号：EP1655667A2

公开(公告)日：2006-05-10

申请号：EP05447243.6

申请日：2005-11-04

Applicant: STMicroelectronics Belgium N.V.

Inventor： Alexandre, Rudolph ,  Charlier, Vincent ,  Rahaga, Tiana ,  Vandersmissen, Yves

IPC: G06F12/06

CPC classification number: G06F9/30149 ,  G06F9/322 ,  G06F9/328 ,  G06F12/0638

Abstract: A code patching device is provided for use with a processor having a read-only memory which stores instruction code and a further memory for storing patch code. A plurality of patch address registers each store an address, in the read-only memory, at which a patch is to be performed. A comparator compares the address of the read-only memory that is being accessed by the processor with the addresses stored in the registers. A control unit selects between code from the read-only memory or patch code from the further memory depending on the comparison. The code patching device can replace, on-the-fly, erroneous lines of code from the read-only memory by corrected ones. During an initialisation process the patch code is loaded into the further memory and the registers are loaded with the addresses which require patching.

Abstract translation: 代码修补装置被提供用于具有存储指令代码的只读存储器和用于存储补丁码的另外的存储器的处理器。 多个补丁地址寄存器每个存储在只读存储器中要在其上执行补丁的地址。 比较器将处理器正在访问的只读存储器的地址与存储在寄存器中的地址进行比较。 控制单元根据比较选择来自只读存储器的代码或来自另外存储器的补丁码。 代码修补设备可以通过修正的代码来替代来自只读存储器的错误的代码行。 在初始化过程中，补丁代码被加载到另外的存储器中，寄存器加载了需要修补的地址。

公开(公告)号：EP1976226A1

公开(公告)日：2008-10-01

申请号：EP08153587.4

申请日：2008-03-28

Applicant: STMicroelectronics Pvt. Ltd. ,  STMicroelectronics Belgium N.V.

Inventor： Gupta, Naresh Kumar ,  Maheshwari, Rajat ,  Charlier, Vincent ,  Vermeire, Gerrit

IPC: H04L29/06

CPC classification number: H04L69/32 ,  H04L69/12 ,  H04W52/0258 ,  H04W76/10 ,  Y02D70/144

Abstract: The present invention discloses a system and a methodology for enhancing performance during wireless communications by reducing system latency, MIPS requirements and power consumption. The present invention discloses a system and method of wireless data communication in which part of upper layer stack processing is performed on a controller to relieve a host processor of some data intensive operations. After the initial connection establishment phase in which the controller retrieves certain information required for data transmission and stores the same locally, the data source provides data directly to the controller without routing the data through the host. The host is relieved of the data processing that needs to be done while the data is being transferred. Hence, the overall latency of the system is improved because of the optimal routing of data traffic. The host can even go to lower power modes while the controller is performing the data operations on behalf of the upper layer stack thereby saving power consumption of the overall system.

Abstract translation: 本发明盘松系统以及用于通过减少系统等待时间，MIPS需求和功率消耗提高在无线通信期间的性能的方法。 本发明盘松动的系统和在上层堆栈处理的哪一部分的无线数据通信的方法中执行的控制器上，以减轻someData密集型操作的主处理器。 初始连接建立阶段，其中控制器在本地检索数据传输所需的某些信息，并存储相同的后，数据源直接提供数据到控制器，而不通过主机路由该数据。 主机被解除了数据处理的根本需求，而数据被传输到完成。 因此，系统的总体等待时间由于数据通信的最优路由，改进。 主机甚至可以到低功率模式的同时，所述控制器被代表上层堆栈从而节省了整个系统的功耗的执行数据操作。

公开(公告)号：EP1959612A1

公开(公告)日：2008-08-20

申请号：EP07003400.4

申请日：2007-02-19

Applicant: STMicroelectronics Belgium N.V.

Inventor： Capretta, Pietro ,  Charlier, Vincent

IPC: H04L12/28 ,  H04L12/56 ,  H04Q7/32

CPC classification number: H04W72/02 ,  H04L1/0003 ,  H04L1/0018 ,  H04L1/1867 ,  H04W24/00 ,  H04W28/22 ,  H04W84/18 ,  H04W88/06

Abstract: A device has a radio transmitter (10) for a first radio link such as a Bluetooth link, having a coexistence controller (60) arranged to communicate with a co located other radio transmitter (30) for another radio link, to enable both radio links to use potentially conflicting transmission frequencies. A link monitor (50) monitors the first radio link, according to an output from the coexistence controller. By making the link monitor dependent on the coexistence controller, it can distinguish between transmission losses caused by the coexistence interface, and those caused by other effects, to reduce the risk of a data rate controller unnecessarily reducing a transmission rate if transmission losses caused by the coexistence control are misinterpreted as a drop in link quality.

Abstract translation: 一种设备具有用于诸如蓝牙链路的第一无线电链路的无线电发射机（10），具有被布置为与另一个无线电链路的位于其他无线电发射机（30）的位置进行通信的共存控制器（60），以使无线电链路 使用潜在的冲突传输频率。 链路监视器（50）根据来自共存控制器的输出监视第一无线电链路。 通过使链路监视器取决于共存控制器，它可以区分由共存接口引起的传输损耗和由其他影响引起的传输损耗，以降低数据速率控制器的风险，不必要地降低传输速率，如果传输损耗由 共存控制被误解为链路质量下降。