公开(公告)号：EP1489521B1

公开(公告)日：2006-05-03

申请号：EP03447153.2

申请日：2003-06-16

Applicant: STMicroelectronics Belgium N.V.

Inventor： Levy, David

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1093 ,  G11C7/1006 ,  G11C7/1078

公开(公告)号：EP1489521A1

公开(公告)日：2004-12-22

申请号：EP03447153.2

申请日：2003-06-16

Applicant: STMicroelectronics Belgium N.V.

Inventor： Levy, David

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G11C7/1093 ,  G11C7/1006 ,  G11C7/1078

Abstract: The present invention is related to a method to control the access of two synchronous busses with asynchronous clocks with unknown relative speed to a single port Random Access Memory (RAM), comprising the steps of :

a) Providing a synchronisation system comprising two busses and a control flip-flop being clocked to the clock of one of said busses,
b) Providing a signal to said control flip-flop requesting a change of the clock of said RAM, resulting in a control flip-flop output signal,
c) Applying said control flip-flop output signal to an inverter circuit yielding a signal INV_out and to a circuit to synchronise said output signal to the clock of the bus not in control of said control flip-flop, yielding a signal CL_SW,
d) Applying the signal INV_out and the signal CL_SW each to a circuit to synchronise to the clock of the other bus yielding signals INV_out_SW and CL_SW_SW, respectively,
e) Applying the signal INV_OUT and the signal CL_SW_SW to a first combinatorial block outputting a signal en1_comb and applying the signal CL_SW and the signal INV_OUT_SW to a second combinatorial block outputting a signal en2_comb,
f) Applying the signal en1_comb and the signal en2_comb each to a falling edge sampling flip-flop, yielding signals en1 and en2, respectively,
g) Applying the signal en1 and the clock of the bus in control of said control flip-flop to an AND gate and the signal en2 and the clock of the other bus to an AND gate, and the outputs of said AND gates to an OR gate,
h) Using the output signal of said OR gate as the clock signal of said RAM
i) Applying the signals en1 and en2 to a combinatorial block that outputs the select signal selecting between said busses to the control and data multiplexers used for communication with said single port RAM.

Abstract translation: 本发明涉及一种用于控制具有与单端口随机存取存储器（RAM）的未知相对速度的异步时钟的两个同步总线的访问的方法，包括以下步骤：a）提供包括两个总线的同步系统和 控制触发器被计时到所述总线中的一个的时钟，b）向所述控制触发器提供请求改变所述RAM的时钟的信号，从而产生控制触发器输出信号，c）应用所述 控制触发器输出信号到逆变器电路，产生一个信号INV_out和一个电路，使所述输出信号与不在所述控制触发器的控制下的总线的时钟同步，产生信号CL_SW，d）应用信号INV_out 和信号CL_SW分别与电路同步的另一总线的时钟，分别产生信号INV_out_SW和CL_SW_SW，e）将信号INV_OUT和信号CL_SW_SW应用于第一组合块输出 信号en1_comb，并将信号CL_SW和信号INV_OUT_SW施加到输出信号en2_comb的第二组合块，f）分别将信号en1_comb和信号en2_comb应用于下降沿采样触发器，分别产生信号en1和en2， g）在所述控制触发器的控制中将信号en1和时钟施加到与门，并将信号en2和另一总线的时钟作为与门，将所述与门的输出连接到OR 门）h）使用所述OR门的输出信号作为所述RAM的时钟信号i）将信号en1和en2施加到组合块，该组合块将在所述总线之间选择的选择信号输出到用于与 表示单端口RAM。