公开(公告)号：EP2339424A1

公开(公告)日：2011-06-29

申请号：EP10196632.3

申请日：2010-12-22

Applicant: STMicroelectronics Design and Application S.R.O.

Inventor： Petenyi, Sandor

IPC: G05F3/30

CPC classification number: G05F3/30

Abstract: An electronic integrated device (100) comprises a signal generation stage (101) arranged to generate a first signal (UVLO) representative of an under voltage lockout logic signal, said signal generation stage comprising a voltage divider block (102) arranged to provide an internal reference voltage signal (VBGI) to a bandgap core group (104) on the basis of a reference signal (VDD), said bandgap core group (104) generating said first signal (UVLO) on the basis of said internal reference voltage signal (VBGI). The bandgap core group (104) further comprises a first generation module (105) arranged to generate a output regulated reference voltage signal (OVBG) on the basis of said internal reference voltage signal, and a second generation module (108) arranged to generate said first signal (UVLO) on the basis of said internal reference voltage signal (VBGI) and a driving signal (ds) obtained by a preliminary processing of said internal reference voltage signal (VBGI) by a bandgap core module (106) included within said band gap core group (104).

Abstract translation: 一种电子集成器件（100）包括被设置成产生第一信号（UVLO）代表一个欠压锁定逻辑信号，所述信号发生级包括布置成提供到内部分压器块（102）的信号发生级（101） 参考电压信号（VBGI）的参考信号（VDD）的基础上的带隙芯组（104），所述带隙芯组（104）产生所述第一信号（UVLO）所述内部基准电压信号的基础上（VBGI ）。 带隙芯组（104）还包括被设置成产生所述内部基准电压信号的基础上，一个输出调节的基准电压信号（OVBG）第一生成模块（105），并布置成产生所述的第二生成模块（108） 第一信号和所述内部基准电压信号（VBGI）和由带隙芯模块（106）通过（VBGI）所述内部基准电压信号的初步处理而获得的驱动信号（DS）的基础上（UVLO）包括在所述带内 间隙芯组（104）。