公开(公告)号：US20250158609A1

公开(公告)日：2025-05-15

申请号：US18541034

申请日：2023-12-15

Applicant: STMicroelectronics International N.V.

Inventor： John Kevin MOORE ,  Kenneth DARGAN ,  Angeliki DELAKOURA

IPC: H03K17/51 ,  G01S7/484 ,  H01S5/042 ,  H03K3/037 ,  H03K5/00 ,  H03K5/131 ,  H03K5/1534 ,  H03K19/00 ,  H03K19/20

Abstract: First digital-components are clocked by a system-clock, and second digital-components are clocked by a gated system-clock. A detection-module identifies detection-events and generates an event-flag in response. A digital-comparator generates a comparator-output based upon comparison of a count-value with a threshold, the comparator-output asserted when the count-value is less than the threshold and is deasserted when the count-value is equal-to or greater-than the threshold. A counter sets the count-value to a predetermined-value upon receipt of the event-flag, and, in response to assertion of the comparator-output, increments the count-value upon each successive rising-edge of the system-clock, but ceases when the comparator-output is deasserted. A clock-gating module releases gating of the gated system-clock so it follows the system-clock, a first number of cycles of the system-clock after assertion of the comparator-output, and reinstates gating of the gated system-clock a second number of cycles of the system-clock after the release of the gating.