公开(公告)号：US20240220278A1

公开(公告)日：2024-07-04

申请号：US18176323

申请日：2023-02-28

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Paolo Sergio ZAMBOTTI ,  Thomas BOESCH ,  Giuseppe DESOLI ,  Wolfgang Johann BETZ ,  David SIORPAES

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: A system includes a host processor, a memory, a hardware accelerator and a configuration controller. The host processor, in operation, controls execution of a multi-stage processing task. The memory, in operation, stores data and configuration information. The hardware accelerator, in operation preforms operations associated with stages of the multi-stage processing task. The configuration controller is coupled to the host processor, the hardware accelerator, and the memory. The configuration controller executes a linked list of configuration operations, for example, under control of a finite state machine. The linked list consists of configuration operations selected from a defined set of configuration operations. Executing the linked list of configuration operations configures the plurality of configuration registers of the hardware accelerator to control operations of the hardware accelerator associated with a stage of the multi-stage processing task. The configuration controller may retrieve the linked list from the memory via a high-speed data bus.

公开(公告)号：US20250165362A1

公开(公告)日：2025-05-22

申请号：US18513380

申请日：2023-11-17

Applicant: STMicroelectronics International N.V.

Inventor： Antonio DE VITA ,  David SIORPAES ,  Thomas BOESCH ,  Giuseppe DESOLI

IPC: G06F11/22

Abstract: A hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (DMA) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.