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    Circuit and method for at speed detection of a word line fault condition in a memory circuit
    1.
    发明授权
    Circuit and method for at speed detection of a word line fault condition in a memory circuit 有权

    公开(公告)号：US11521697B2

    公开(公告)日：2022-12-06

    申请号：US16742292

    申请日：2020-01-14

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir Kumar ,  Abhishek Pathak

    IPC: G11C29/38 ,  G11C29/44 ,  G11C8/10

    Abstract: A row decoder located on one side of a memory array selectively drives word lines in response to a row address. A word line fault detection circuit located on an opposite side of the first memory array operates to detect an open word line fault between the opposed sides of the memory array. The word line fault detection circuit includes a first clamp circuit that operates to clamp the word lines to ground. An encoder circuit encodes signals on the word lines to generate an encoded address. The encoded address is compared to the row address by a comparator circuit which sets an error flag indicating the open word line fault has been detected if the encoded address does not match the row address.

    Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory
    3.
    发明授权
    Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory 有权

    公开(公告)号：US10998077B2

    公开(公告)日：2021-05-04

    申请号：US16702744

    申请日：2019-12-04

    Applicant: STMicroelectronics International N.V.

    Inventor： Rohit Bhasin ,  Shishir Kumar ,  Tanmoy Roy ,  Deepak Kumar Bihani

    IPC: G11C29/38 ,  G11C29/14

    Abstract: A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.

    Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier
    4.
    发明授权
    Robust adaptive method and circuit for controlling a timing window for enabling operation of sense amplifier 有权

    公开(公告)号：US11195576B2

    公开(公告)日：2021-12-07

    申请号：US16596989

    申请日：2019-10-09

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir Kumar ,  Bhupender Singh

    IPC: G11C11/419 ,  G11C11/417

    Abstract: A sense amplifier enable signal and a tracking signal are generated in response to an indication that a sufficient voltage difference has developed across bit lines of a memory. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal is propagated along a first U-turn signal line that extends parallel to rows of the memory array and is coupled to sense amplifiers arranged in a row to generate a sense amplifier enable return signal. The tracking signal is propagated along a second U-turn signal line extending parallel to columns of the memory array to generate a tracking return signal. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. Timing of the trailing edge of the pulse width is controlled by the reset signal.

    SRAM read multiplexer including replica transistors
    5.
    发明授权
    SRAM read multiplexer including replica transistors 有权

    公开(公告)号：US10311944B2

    公开(公告)日：2019-06-04

    申请号：US16025647

    申请日：2018-07-02

    Applicant: STMicroelectronics International N.V.

    Inventor： Dhori Kedar Janardan ,  Abhishek Pathak ,  Shishir Kumar

    IPC: G11C5/06 ,  G11C11/417

    Abstract: A first transistor has a first conduction terminal coupled to a second bit line, a second conduction terminal coupled to a bit line node, and a control terminal biased by a second control signal. A second transistor has a first conduction terminal coupled to a second complementary bit line, a second conduction terminal coupled to a complementary bit line node, and a control terminal biased by the second control signal. A first replica transistor has a first conduction terminal coupled to the second bit line, a second conduction terminal coupled to the complementary bit line node, and a control terminal biased such that the first replica transistor is off. A second replica transistor has a first conduction terminal coupled to the second complementary bit line, a second conduction terminal coupled to the bit line node, and a control terminal biased such that the second replica transistor is off.

    System and method for a pulse generator
    6.
    发明授权
    System and method for a pulse generator 有权
    脉冲发生器的系统和方法

    公开(公告)号：US09590602B2

    公开(公告)日：2017-03-07

    申请号：US14304357

    申请日：2014-06-13

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir Kumar ,  Tanmoy Roy

    IPC: H03K5/01 ,  G11C8/18 ,  G11C7/22

    CPC classification number: H03K5/01 ,  G11C7/222 ,  G11C8/18

    Abstract: According to an embodiment, a method of generating a clock pulse includes receiving a leading edge at a clock input at a time when an enable signal is active, generating an edge at a clock output based on the received leading edge at the clock input, latching a logic value corresponding to the edge at the clock output, preventing changes at the clock input from affecting the latched logic value after the logic value is latched, resetting the latched logic value after a first delay time, and maintaining the reset logic value until a second edge is received at the clock input. The second edge at the clock input matches the leading edge at the clock input.

    Abstract translation: 根据实施例，一种产生时钟脉冲的方法包括在使能信号有效时在时钟输入端处接收前沿，在时钟输出端基于接收到的前沿产生时钟输出的边沿，锁存 对应于时钟输出端的逻辑值，防止在逻辑值被锁存之后时钟输入的变化影响锁存的逻辑值，在第一延迟时间之后复位锁存的逻辑值，并保持复位逻辑值直到 在时钟输入端接收第二个边沿。 时钟输入端的第二个边沿与时钟输入端的前沿匹配。

    Programmable delay introducing circuit in self timed memory
    7.
    发明授权
    Programmable delay introducing circuit in self timed memory 有权
    自定时存储器中的可编程延迟引入电路

    公开(公告)号：US09147453B2

    公开(公告)日：2015-09-29

    申请号：US14532174

    申请日：2014-11-04

    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

    Inventor： Nishu Kohli ,  Mudit Bhargava ,  Shishir Kumar

    IPC: H05B1/02 ,  G11C7/22 ,  G11C7/06 ,  G11C7/08 ,  G11C29/12 ,  G11C29/14 ,  G11C29/50

    CPC classification number: G11C7/227 ,  G11C7/06 ,  G11C7/08 ,  G11C7/22 ,  G11C7/222 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

    Abstract: Delays are introduced in self-timed memories by introducing a capacitance on the path of a signal to be delayed. The capacitances are realized by using idle-lying metal layers in the circuitry. The signal to be delayed is connected to the idle-lying capacitances via programmable switches. The amount of delay introduced depends on the capacitance introduced in the path of signal, which in turn depends on state of the switches. The state of the switches is controlled by delay codes provided externally to the delay introducing circuitry. Since idle-lying metal capacitances are utilized, the circuitry can be implemented using a minimum amount of additional hardware. Also, the delay provided by the circuitry is a function of memory cell SPICE characteristics and core parasitic capacitances.

    Abstract translation: 通过在要延迟的信号的路径上引入电容，在自定时存储器中引入延迟。 电容通过在电路中使用空闲的金属层来实现。 要延迟的信号通过可编程开关连接到空载电容。 引入的延迟量取决于在信号路径中引入的电容，这又取决于开关的状态。 开关的状态由延迟引入电路外部提供的延迟代码来控制。 由于利用空闲位置的金属电容，所以可以使用最小量的附加硬件实现电路。 此外，由电路提供的延迟是存储器单元SPICE特性和内核寄生电容的函数。

    SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY
    8.
    发明申请
    SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY 有权
    自定义存储器的选择性双循环写操作

    公开(公告)号：US20150029795A1

    公开(公告)日：2015-01-29

    申请号：US13949449

    申请日：2013-07-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Nishu Kohli ,  Shishir Kumar

    IPC: G11C7/22

    CPC classification number: G11C11/419 ,  G11C7/227

    Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

    Abstract translation: 在第一存储器访问周期期间在第一行和列处对存储器的第一单元执行写入。 在紧接着的第二存储器访问周期期间，在第二行和列处对第二单元进行存储器存取操作。 如果存储器访问是从第二单元读取并且第二行与第一行相同，或者如果存储器访问是对第二单元的写入，并且第二行与第一行和第二列相同 与第一列不同，则在第二存储器访问周期期间执行同时操作。 同时操作是第二单元（用于读取或写入）的访问以及从第一存储器访问周期写入操作重新写入数据到第一单元。

    Circuit for detection of single bit upsets in generation of internal clock for memory
    10.
    发明授权
    Circuit for detection of single bit upsets in generation of internal clock for memory 有权

    公开(公告)号：US11025252B2

    公开(公告)日：2021-06-01

    申请号：US16578487

    申请日：2019-09-23

    Applicant: STMicroelectronics International N.V.

    Inventor： Shishir Kumar ,  Tanuj Kumar ,  Deepak Kumar Bihani

    IPC: H03K19/003

    Abstract: A failure determination circuit includes a latch circuit that receives an internal clock from a clock latch that rises in response to an external clock rising. In response to a rising edge of the external clock, the circuit generates a rising edge of a fault flag. In response to a rising edge of the internal clock if it occurs, the fault flag falls. The fault flag is then latched. The latched fault flag indicates a single bit upset in the clock latch if the falling edge of the fault flag was not generated prior to latching, if the clock latch is in an active mode, and indicates a single bit upset in the clock latch if the falling edge of the fault flag was generated prior to latching, if the clock latch is in an inactive mode.

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