公开(公告)号：EP1083659A1

公开(公告)日：2001-03-14

申请号：EP00307665.0

申请日：2000-09-05

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/018521

Abstract: A level shifter uses a current mirror as a current switch connected to the drains of two oppositely-driven FETs. A switch selectively connects the current mirror to its power supply so that no quiescent DC current flows.

Abstract translation: 电平转换器使用电流镜作为连接到两个相对驱动的FET的漏极的电流开关。 开关选择性地将电流镜连接到其电源，使得没有静态DC电流流动。

公开(公告)号：EP1039472B1

公开(公告)日：2006-01-11

申请号：EP00301535.1

申请日：2000-02-28

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/062

公开(公告)号：EP1235349A1

公开(公告)日：2002-08-28

申请号：EP01301785.0

申请日：2001-02-27

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: H03K3/356 ,  H03K19/096 ,  G11C7/06 ,  H03K5/24

CPC classification number: H03K5/249 ,  G11C7/065 ,  H03K3/356139 ,  H03K5/1534 ,  H03K19/0963

Abstract: To establish whether a precharged node remains isolated or alternatively is subject to discharge, the conventional circuit allows uncertainty. For a period after evaluation starts, the conventional circuit will give a tentative result that may subsequently turn out to be wrong. During evaluation power is dissipated.
According to the invention a differential offset dynamic comparator and timing circuit are used. Because the comparator has an offset, much smaller deviations from the precharge potential can be sensed: because it is dynamic, it does not consume steady state current. The timing circuit permits precise knowledge of when to look at the output: before the timing period has elapsed, the result is known to be invalid.

Abstract translation: 为了确定预充电节点是否保持隔离或者可替代地进行放电，常规电路允许不确定性。 在评估开始一段时间后，常规电路将给出一个可能随后证明是错误的初步结果。 评估过程中耗电。 根据本发明，使用差分偏移动态比较器和定时电路。 因为比较器具有偏移，所以可以感测到与预充电电位相差很小的偏差：因为它是动态的，它不消耗稳态电流。 定时电路可以准确了解何时查看输出：在定时周期过去之前，已知结果无效。

公开(公告)号：EP1098439A1

公开(公告)日：2001-05-09

申请号：EP00309662.5

申请日：2000-11-01

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: H03K17/687

CPC classification number: H01L29/0634 ,  H03K3/356113 ,  H03K17/102

Abstract: A switching circuit is discussed that has an improved switching time in comparison with switching circuits of a known type. The circuit comprises three switches (101,104,106) connected in series, the first switch (101) being connected to an upper power supply and the third switch (106) being connected to a lower power supply. The output of the circuit is connected to a circuit node (N) located at the connection between the second and third switch. The input to the switching circuit is also connected to the third switch and additionally connected to a control circuit (102) which provides a further output to control the first switch. The second switch (104) is responsive to the voltage at the circuit node such that the second switch only conducts when the voltage at the output node falls below the upper supply voltage. This has the effect that the first switch is effectively isolated from the third switch during switching and allows a time delay during which the first switch is switched off under control of the control circuit and the second switch switches on. The provision of the voltage dependent second switch eliminates any 'current battles' occurring between the first and third switch during switching.

Abstract translation: 讨论了与已知类型的开关电路相比具有改进的开关时间的开关电路。 电路包括串联连接的三个开关（101,104,106），第一开关（101）连接到上电源，第三开关（106）连接到下电源。 电路的输出连接到位于第二和第三开关之间的连接处的电路节点（N）。 开关电路的输入也连接到第三开关，并另外连接到控制电路（102），控制电路提供另外的输出来控制第一开关。 第二开关（104）响应于电路节点处的电压，使得第二开关仅在输出节点处的电压低于上电源电压时才导通。 这具有这样的效果：在开关期间第一开关与第三开关有效隔离，并且允许第一开关在控制电路的控制下被切断并且第二开关导通的时间延迟。 提供依赖于电压的第二开关消除了在切换期间在第一和第三开关之间发生的任何“当前的战斗”。

公开(公告)号：EP1083659B1

公开(公告)日：2007-08-29

申请号：EP00307665.0

申请日：2000-09-05

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: H03K19/003 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/018521

公开(公告)号：EP1028432B1

公开(公告)日：2006-11-29

申请号：EP00300785.3

申请日：2000-02-01

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/08

公开(公告)号：EP1239487A1

公开(公告)日：2002-09-11

申请号：EP01302064.9

申请日：2001-03-06

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C7/20 ,  G11C11/419 ,  G11C11/4072

CPC classification number: G11C7/20 ,  G11C11/419

Abstract: It is often desirable to write a single value to all the cells in a memory. Usually this is done using separate reset circuitry. The normal write transistor provided for each column is dimensioned to be big enough to reliably overcome the pull-up of the p FET of a cell, and thus are not capable of writing to plural cells at once. If the write transistors are made larger, space is wasted and the memory is slower due to the extra capacitance.
In the embodiment all cells per column are connected to the positive rail via a single switch, and that switch turned off while writing to all cells. The switch is then turned on again which allows the cells to become actually reset. This allows for use of standard or optimised RAM cells to have flash clear.

Abstract translation: 通常希望将单个值写入存储器中的所有单元。 通常这是使用单独的复位电路完成的。 为每列提供的正常写入晶体管的尺寸被设计为足够大以可靠地克服单元的p FET的上拉，因此不能一次写入多个单元。 如果写入晶体管较大，则由于额外的电容，空间被浪费并且存储器较慢。 在该实施例中，每列的所有单元通过单个开关连接到正轨，并且该开关在写入所有单元时关闭。 然后再次打开开关，这允许电池实际上重置。 这允许使用标准或优化的RAM单元来清除闪存。

公开(公告)号：EP1083574A1

公开(公告)日：2001-03-14

申请号：EP00306901.0

申请日：2000-08-11

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A miss detector for a content addressable memory has plural input lines connected across points with the memory output lines. The detector input lines are disposed in pairs of true and false lines, and gating circuitry gates together the true and false pairs to provide a miss error message.

Abstract translation: 用于内容可寻址存储器的未命中检测器具有连接到存储器输出线的点的多个输入线。 检测器输入线以真线和虚线成对配置，并且门控电路将真假对组合在一起以提供错误错误信息。

公开(公告)号：EP1039472A1

公开(公告)日：2000-09-27

申请号：EP00301535.1

申请日：2000-02-28

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C7/06

CPC classification number: G11C7/067 ,  G11C7/062

Abstract: A sense amplifier circuit has two inputs for connection to complementary bit lines and an output terminal. The circuit comprises control circuitry responsive to control input for selectively tristating the output terminal.

Abstract translation: 读出放大器电路具有用于连接到互补位线和输出端的两个输入。 电路包括响应于控制输入的控制电路，用于选择性地将输出端子三态化。

公开(公告)号：EP1028432A1

公开(公告)日：2000-08-16

申请号：EP00300785.3

申请日：2000-02-01

Applicant: STMicroelectronics Limited

Inventor： Barnes, William Bryan

IPC: G11C8/00

CPC classification number: G11C8/10 ,  G11C8/08

Abstract: A wordline driver has enable circuitry optimized for positive-going input transitions and disable circuitry optimized for transitions in a disable input which would cause the output to become disabled. The optimization is achieved by suitably dimensioning the transistors in the respective enable and disable circuits for suitable current-carrying ability.

Abstract translation: 字线驱动器使电路能够针对正向输入转换进行优化，并禁用优化用于禁用输入转换的电路，从而导致输出被禁用。 通过适当确定各个启用和禁用电路中的晶体管的尺寸以获得合适的载流能力来实现优化。