Abstract:
An image sensor array 12 of active pixel elements 17 arranged in rows and columns, where each column has an output circuit 18 for reading out pixel image signals comprising a pair of sample capacitors 34, 36, a switching means 38, 40 operable in conjunction with pixel switches 24, 26, 28 to apply pixel voltages to the sample capacitors 34, 36, and one or more optically masked pixels 19 such that output image signals obtained from said optically masked pixels 19 represent substantially only the column FPN includes image processing means 14 for recording the column FPN for each column from said optically masked pixels 19; recording the image signal from said sensor array of active pixels 17; and subtracting the column FPN column-wise from the image signal.