公开(公告)号：EP1263139A3

公开(公告)日：2006-07-05

申请号：EP02253697.3

申请日：2002-05-27

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Elliot, Paul

IPC: H03K17/00 ,  G06F1/08

CPC classification number: G06F1/08 ,  H03K5/1252 ,  H03K17/005

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed (20,22) relative to clock A to give a signal P, is then retimed (24,26) relative to clock B to give a signal Q, and finally is retimed (28,30) relative to clock A to give a signal R. Selector circuitry (34,40,42) operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate (34), are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

公开(公告)号：EP1263139A2

公开(公告)日：2002-12-04

申请号：EP02253697.3

申请日：2002-05-27

Applicant: STMicroelectronics Limited

Inventor： Dellow, Andrew ,  Elliot, Paul

IPC: H03K17/00 ,  G06F1/08

CPC classification number: G06F1/08 ,  H03K5/1252 ,  H03K17/005

Abstract: A clock source selector for selecting either a first clock signal A or a second clock signal B in accordance with a switch request signal includes three retiming circuits each consisting of two clocked flip-flops. The switch request signal is first retimed (20,22) relative to clock A to give a signal P, is then retimed (24,26) relative to clock B to give a signal Q, and finally is retimed (28,30) relative to clock A to give a signal R. Selector circuitry (34,40,42) operates such that when signal Q is asserted, the second clock signal B is output, when neither signal P nor signal R, as combined by a NOR gate (34), are asserted, the first clock signal A is output, and at other times a zero level is output. The clock source selector can be used in an integrated circuit to form a glitch-free multiplexer.

Abstract translation: 用于根据切换请求信号选择第一时钟信号A或第二时钟信号B的时钟源选择器包括三个重新定时电路，每个由两个时钟触发器组成。 首先，切换请求信号相对于时钟A被重新定时（20,22），以给出信号P，相对于时钟B被重新定时（24,26），给出一个信号Q，最后被重定时（28,30）相对 到时钟A给出信号R.选择器电路（34,40,42）的操作使得当信号Q被确定时，第二时钟信号B被输出，当信号P和信号R都不由NOR门（ 34）被断言，第一时钟信号A被输出，并且在其他时间输出零电平。 时钟源选择器可用于集成电路中以形成无毛刺多路复用器。