公开(公告)号：EP1601131B1

公开(公告)日：2007-07-11

申请号：EP04253042.8

申请日：2004-05-24

Applicant: STMicroelectronics Limited

Inventor： Hutson, Matthew Peter

IPC: H04L7/02

CPC classification number: H04L7/02

公开(公告)号：EP1601131A1

公开(公告)日：2005-11-30

申请号：EP04253042.8

申请日：2004-05-24

Applicant: STMicroelectronics Limited

Inventor： Hutson, Matthew Peter

IPC: H04L7/02

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列到多个其他时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及选通电路，用于接收更新信号，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。