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    A dividing circuit for dividing by even numbers
    2.
    发明公开
    A dividing circuit for dividing by even numbers 有权
    Teilerschaltung zum Teilen durch gerade Zahlen

    公开(公告)号：EP0926832A1

    公开(公告)日：1999-06-30

    申请号：EP98310168.4

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： Monk, Trevor

    IPC: H03K23/54 ,  H03K23/66 ,  H03K23/44 ,  H03L7/183

    CPC classification number: H03K23/66 ,  H03K23/44 ,  H03K23/54 ,  H03K23/667 ,  H03L7/183

    Abstract: A dividing circuit comprises, connected in a ring, a plurality M of transistor stages (S1-S4), where M is an even integer. Each transistor stage comprises an input node, a clock node and an output node. A tri-state inverter stage (S5) has an input node connected to the output node of the preceding transistor stage in the ring (S4), an enable node connected to the clock nodes of the transistor stages, and an output node (CLKOUT) connected to the input node (I1) of the subsequent transistor stage in the ring. Each transistor stage comprises a first pair of transistors of a first conductivity type (T1,T2) connected in series between a first voltage level and an output node and a second pair of transistors of a second conductivity type (T3,T4) connected in series between a second voltage level and said output node, wherein control nodes of a first transistor (T1,T4) of each said transistor pair are connected together to provide the input node (I1) for the stage, and control nodes of a second transistor (T2,T3) of each said transistor pair are connected together to provide the clock node (CLKIN) for the stage, whereby when an input clock signal is applied to the clock nodes of the transistor stages, an output signal is generated at the output node of the tri-state inverter in which each cycle represents M cycles of the input clock signal.

    Abstract translation: 分频电路包括以环形连接多个M个晶体管级（S1-S4），其中M为偶数整数。 每个晶体管级包括输入节点，时钟节点和输出节点。 三态反相器级（S5）具有连接到环（S4）中的前一晶体管级的输出节点的输入节点，连接到晶体管级的时钟节点的使能节点和输出节点（CLKOUT） 连接到环中随后的晶体管级的输入节点（I1）。 每个晶体管级包括串联连接在第一电压电平和输出节点之间的第一导电类型（T1，T2）的第一对晶体管和第二导电类型（T3，T4）的第二对晶体管串联连接 在第二电压电平和所述输出节点之间，其中每个所述晶体管对的第一晶体管（T1，T4）的控制节点连接在一起以提供用于所述级的输入节点（I1）和第二晶体管的控制节点 T2，T3）连接在一起，以为该级提供时钟节点（CLKIN），由此当输入时钟信号施加到晶体管级的时钟节点时，在输出节点处产生输出信号 其中每个周期表示输入时钟信号的M个周期。

    A programmable divider circuit
    3.
    发明公开
    A programmable divider circuit 有权
    Programmierbare Teilerschaltung

    公开(公告)号：EP0926834A1

    公开(公告)日：1999-06-30

    申请号：EP98310160.1

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： Monk, Trevor

    IPC: H03K23/66 ,  H03K23/54

    CPC classification number: H03L7/183 ,  H03K23/544 ,  H03K23/66 ,  H03K23/667

    Abstract: A programmable dividing circuit comprises a first plurality N of similar transistor stages (B1,B2) connected in a divide-by-N sequence, where N is an odd integer, the transistor stages being configured so that when the output of the last stage is supplied to the first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated which has one cycle for every N cycles of a clock signal applied to the transistor stages, a tri-state inverter (T) selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages (B1,B3,B4), where M is an even integer, and wherein the second plurality includes at least some of said first plurality of transistor stages, including said first stage, whereby when the output of the last stage in the divide-by-M sequence is supplied to the first stage, the circuit operates as a divide-by-M circuit in which an output signal is generated which has one cycle for every M cycles of a clock signal applied to the transistor stages, and a switching circuit (MUX) having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence whereby the circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

    Abstract translation: 可编程分频电路包括以N分频序列连接的第一多个N个相似的晶体管级（B1，B2），其中N为奇整数，晶体管级被配置为使得当最后级的输出为 按照序列提供给第一级，分频电路作为N分频电路工作，其中产生输出信号，对于施加到晶体管级的时钟信号的每N个周期，具有一个周期，三态 逆变器（T）可以以M分频序列与第二多个M个晶体管级（B1，B3，B4）连接，其中M是偶数整数，并且其中第二多个包括所述第一多个 包括所述第一级，由此当M分频序列中的最后级的输出被提供给第一级时，该电路作为产生输出信号的除M电路工作 对于a的每个M个周期，其具有一个周期 施加到晶体管级的时钟信号，以及具有至少两个输入的开关电路（MUX），并且被布置为以N分频或分频方式选择性地将最后级的输出连接到第一级， M序列，由此电路可以被编程为以N分频或M分频电路工作。

    A dividing circuit and transistor stage therefor
    4.
    发明公开
    A dividing circuit and transistor stage therefor 审中-公开
    Teilerschaltung und Transistorstufedafür

    公开(公告)号：EP0926833A1

    公开(公告)日：1999-06-30

    申请号：EP98310190.8

    申请日：1998-12-11

    Applicant: STMicroelectronics Limited

    Inventor： Monk, Trevor

    IPC: H03K23/54 ,  H03K23/44 ,  H03K23/66 ,  H03L7/183

    CPC classification number: H03L7/183 ,  H03K23/44 ,  H03K23/544 ,  H03K23/66

    Abstract: A dividing circuit comprises a plurality (N) of transistor stages connected in a ring. Each stage comprises a first pair of transistors of a first conductivity type (T1,T2) connected in series between a first voltage level (Vdd) and an output node (O1), a second pair of transistors of a second conductivity type (T3,T4) connected in series between a second voltage level and said output node (O1),
       wherein control nodes of a first transistor (T1,T4) of each said transistor pair are connected together to provide an input node (I1) for the stage, and control nodes of a second transistor (T2,T3) of each said transistor pair are connected together to provide a clock node (CLK IN) for the stage, wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than the duty cycle of said clock signal.

    Abstract translation: 分频电路包括以环形连接的多个（N）个晶体管级。 每个级包括串联连接在第一电压电平（Vdd）和输出节点（O1）之间的第一导电类型（T1，T2）的第一对晶体管，第二导电类型的第二对晶体管（T3， T4）串联连接在第二电压电平和所述输出节点（O1）之间，其中每个所述晶体管对的第一晶体管（T1，T4）的控制节点连接在一起以提供用于该级的输入节点（I1） 并且每个所述晶体管对的第二晶体管（T2，T3）的控制节点连接在一起以为所述级提供时钟节点（CLK IN），其中每一级的输入节点连接到前一级的输出节点 由此在每个所述输出节点处产生输出信号，每个周期的输出信号表示施加到级的所述时钟节点的时钟信号的N个周期，输出信号的占空比接近50％ 所述时钟信号的占空比。

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