公开(公告)号：EP1321984A2

公开(公告)日：2003-06-25

申请号：EP01307231.9

申请日：2001-08-24

Applicant: STMicroelectronics Limited

Inventor： Thies, William ,  Froidevaux, Nicolas

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.

Abstract translation: 公开了一种制造半导体电路的方法，其与传统的电路布局相比具有区域节省。 IO单元被布置成宽度乘以因子，但具有相应减小的高度。 与常规安排相比，ESD保护电路以降低的速度被包括在内。 通过占用由ESD电路与IO电路一起使用的半导体区域来实现节省空间。 ESD保护保持在不同的位置。

公开(公告)号：EP1545008A1

公开(公告)日：2005-06-22

申请号：EP03258081.3

申请日：2003-12-19

Applicant: STMicroelectronics Limited

Inventor： Thies, William ,  Lawley, Chris

IPC: H03L7/197

CPC classification number: H03L7/095 ,  H03L7/0891 ,  H03L7/10 ,  H03L7/197 ,  Y10S331/02

Abstract: A phase locked loop (PLL) circuit comprising: feedback division circuitry for receiving an output signal, the feedback division circuitry arranged to divide the output signal by a first division factor in a first mode of operation, and a second division factor in a second mode of operation.

Abstract translation: 一种锁相环（PLL）电路，包括：用于接收输出信号的反馈分频电路，所述反馈分频电路经布置以将输出信号除以第一操作模式的第一分频因子，以及在第二模式中的第二分频因子 的操作。

公开(公告)号：EP1321984A3

公开(公告)日：2004-01-14

申请号：EP01307231.9

申请日：2001-08-24

Applicant: STMicroelectronics Limited

Inventor： Thies, William ,  Froidevaux, Nicolas

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/06153

Abstract: A method of producing a semiconductor circuit is disclosed with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.