公开(公告)号：EP1544631B1

公开(公告)日：2007-06-20

申请号：EP03257952.6

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185

CPC classification number: G01R31/318563 ,  G01R31/318536

公开(公告)号：EP1544630B1

公开(公告)日：2008-05-14

申请号：EP03257951.8

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185

CPC classification number: G01R31/318563 ,  G01R31/318536

公开(公告)号：EP1544633A1

公开(公告)日：2005-06-22

申请号：EP03257954.2

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185

CPC classification number: G01R31/318536 ,  G01R31/318563

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between said at least one test input and said test control circuitry, said multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of said plurality of portions.

Abstract translation: 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试信号; 以及在所述至少一个测试输入和所述测试控制电路之间的多路复用器，所述多路复用器具有至少一个控制输入，由此所述多路复用器可控制以将测试信号引导到所述多个部分中的一个。

公开(公告)号：EP1544632A1

公开(公告)日：2005-06-22

申请号：EP03257953.4

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185 ,  G01R31/3187

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between said at least one test input and circuitry to be tested; wherein said test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和待测电路之间的测试控制电路; 其中所述测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：EP1544631A1

公开(公告)日：2005-06-22

申请号：EP03257952.6

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals, said circuit having a test mode in which one or more of said plurality of portions are testable, wherein said circuit has a reset mode which has priority over said test mode.

Abstract translation: 一种集成电路，包括多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置为接收测试信号，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优先于所述测试模式的复位模式。

公开(公告)号：EP1544630A1

公开(公告)日：2005-06-22

申请号：EP03257951.8

申请日：2003-12-17

Applicant: STMicroelectronics Limited

Inventor： Warren, Bob

IPC: G01R31/3185

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test data; wherein said test data is clocked in a plurality of time slots, with test data for different ones of said plurality of portions being allocated to different time slots.

Abstract translation: 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试数据; 其中所述测试数据在多个时隙中计时，所述多个部分中的不同部分的测试数据被分配给不同的时隙。