公开(公告)号：EP1271783A2

公开(公告)日：2003-01-02

申请号：EP02013243.7

申请日：2002-06-17

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

Abstract translation: 一种用于简化可编程存储器，以在FPGA中逻辑接口结构的提议。 被检查的接口做了它分离为帧内PLB（可编程逻辑块）从RAM地址，数据和控制线路由通用路由架构。 可编程逻辑块和FPGA的输入 - 输出资源使用专用的直接互连访问嵌入式存储器或RAM。 论文直接互连的主要部分从可编程逻辑块在RAM的附近表面。 输入 - 输出（IO）垫/路由和RAM块之间的其余运行。 专用总线的路由架构被提供给俱乐部的记忆来模拟较大RAM块。 该总线路由是专门RAM块之间的互连，并从PLB布线资源隔离。

公开(公告)号：EP1271783A3

公开(公告)日：2004-11-03

申请号：EP02013243.7

申请日：2002-06-17

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K19/17736 ,  H03K19/17744

Abstract: A structure for simplifying the programmable memory to logic interface in FPGAs is proposed. The interface is such that it isolates the general purpose routing architecture for intra-PLB (Programmable Logic Blocks) routing from the RAM address, data and control lines. The programmable logic blocks and the input-output resources of the FPGA access the embedded memory or RAM using dedicated direct interconnects. A major part of these direct interconnects surface from programmable logic blocks in vicinity of the RAM. The rest run between the input-output (IO) pads/routing and the RAM blocks. A dedicated bus-routing architecture is provided to club the memories to emulate larger RAM blocks. This bus routing is devoted to interconnection among RAM blocks and is isolated from the PLB routing resources.

公开(公告)号：EP1233517A1

公开(公告)日：2002-08-21

申请号：EP02002800.7

申请日：2002-02-07

Applicant: STMicroelectronics Ltd.

Inventor： Bal, Ankur

IPC: H03K19/177

CPC classification number: H03K19/17776

Abstract: A system for rapid configuration of reconfigurable devices with a plurality of latches (2a). The number of clock cycles for loading the configuration data are reduced by a substantial amount and the fidelity of data loaded into the configuration latches is high. The invention also incorporates procedures for configuring multiple reconfigurable devices, which are similar to the prevalent "Daisy chain" technique. The system comprises a configuration memory (11) including a plurality of memory elements (2a); a write control shift register (1) for selecting a logically continuous set of bits in the configuration memory (11); a decoder (8) for selecting one column (3) at a time of the programmable logic device; and pass transistors (10a) for connecting the input of an own memory element (2a) storing said bit to a logic '0' or a logic '1' level.

Abstract translation: 一种用于快速配置具有多个闩锁（2a）的可重新配置的装置的系统。 用于加载配置数据的时钟周期数量减少了大量，并且加载到配置锁存器中的数据的保真度很高。 本发明还包括用于配置多个可重新配置设备的过程，其类似于普遍的“菊花链”技术。 该系统包括配置存储器（11），其包括多个存储元件（2a）; 写入控制移位寄存器（1），用于选择配置存储器（11）中逻辑上连续的位组; 用于在可编程逻辑器件的时间选择一列（3）的解码器（8）; 并将用于将存储所述位的自己的存储元件（2a）的输入连接到逻辑“0”或逻辑“1”电平的晶体管（10a）。