公开(公告)号：EP1209687A3

公开(公告)日：2002-09-18

申请号：EP01127859.5

申请日：2001-11-22

Applicant: STMicroelectronics Ltd.

Inventor： Dubey, Prashant

IPC: G11C11/41 ,  G11C11/418 ,  G11C11/419 ,  G06F17/50

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419

Abstract: This invention relates to a synthesizable, synchronous static RAM comprising custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice and a semi-custom built control clock generation section, which is connected to said semi-custom built decoder and IO section. The arrangement being such as to provides high speed access, easy testability and asynchronous initialization capabilities while reducing design time in a size that is significantly smaller than existing semi custom or standard cell base memory design.

公开(公告)号：EP1209687A2

公开(公告)日：2002-05-29

申请号：EP01127859.5

申请日：2001-11-22

Applicant: STMicroelectronics Ltd.

Inventor： Dubey, Prashant

IPC: G11C11/41 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/41 ,  G11C11/419

Abstract: This invention relates to a synthesizable, synchronous static RAM comprising custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice and a semi-custom built control clock generation section, which is connected to said semi-custom built decoder and IO section. The arrangement being such as to provides high speed access, easy testability and asynchronous initialization capabilities while reducing design time in a size that is significantly smaller than existing semi custom or standard cell base memory design.

Abstract translation: 本发明涉及一种可合成的同步静态RAM，其包括定制的内存单元和位片形式的半定制IO /预充电部分，连接到所述位片的半定制内置解码器和半定制内置控制时钟生成部分 ，其连接到所述半定制内置解码器和IO部分。 这种安排是提供高速访问，易于测试和异步初始化功能，同时减少了设计时间，其尺寸明显小于现有的半定制或标准单元基础存储器设计。