公开(公告)号：EP0901080B1

公开(公告)日：2005-06-15

申请号：EP98307033.5

申请日：1998-09-02

Applicant: STMicroelectronics Ltd.

Inventor： Jones, Andrew Michael ,  Barnes, Peter Malcolm

IPC: G06F13/16

CPC classification number: G06F12/0215 ,  G06F13/1631

公开(公告)号：EP0945805A1

公开(公告)日：1999-09-29

申请号：EP99301960.3

申请日：1999-03-15

Applicant: Stmicroelectronics, Ltd.

Inventor： Jones, Andrew Michael

IPC: G06F12/08

CPC classification number: G06F12/0837 ,  G06F12/0815

Abstract: A computer system has a plurality of processors each for executing a sequence of instructions and at least one of the processors having a cache memory associated therewith. A memory provides an address space of that processor where data items are stored for use by all of the processors. A behaviour store holds in association with the address of each item a cache behaviour identifying the cacheable behaviour of the item, the cacheable behaviours including a software coherent behaviour and an automatically coherent behaviour. When a cache coherency operation is instigated by a cache coherency instruction, the operation is effected dependent on the cacheable behaviour of the specified address of the item.
A method of modifying the coherency status of a cache in this manner is also described.

Abstract translation: 计算机系统具有多个处理器，每个处理器用于执行指令序列，并且至少一个处理器具有与其相关联的高速缓冲存储器。 存储器提供该处理器的地址空间，其中存储数据项以供所有处理器使用。 行为存储与每个项目的地址相关联地存储识别项目的可缓存行为的缓存行为，可缓存行为包括软件相关行为和自动相关行为。 当缓存一致性操作由高速缓存一致性指令引发时，该操作取决于项目的指定地址的可缓存行为。 还描述了以这种方式修改高速缓存的相关性状态的方法。