公开(公告)号：EP1841073A1

公开(公告)日：2007-10-03

申请号：EP06006521.6

申请日：2006-03-29

Applicant: STMicroelectronics N.V.

Inventor： Kienle, Franck ,  Wehn, Norbert ,  Brack, Torben

IPC: H03M13/11

CPC classification number: H03M13/3905 ,  H03M13/1165 ,  H03M13/1197 ,  H03M13/3972

Abstract: Method of decoding LDPC codes such as IRA codes used in the DVB-S2 standard, the code graph comprising first variable nodes (systematic), second variable nodes (parity) having a degree two, and check nodes connected to second variable nodes by a zigzag connectivity, the method comprising
a) grouping the check nodes into at least one group, the check nodes of each group being connected by variable nodes called internal variable nodes,
b) performing for each group (GR i ) the following sub-steps b1) and b2):
b1) jointly updating (71) all the check nodes of said group by using an algorithm of the Maximum-A-Posteriori (MAP) type on a two-state trellis,
b2) updating (72,73) all the first variable nodes and all the second variable nodes (PN i-1,i ; PN i,i+1 ) connected to said group except said at least one internal second variable node,
c) iteratively repeating step b)
When using a plurality of groups, a corresponding plurality of trellis windows are LogMAP decoded without training period since connecting parity nodes are updated according the sum-product algorithm.

Abstract translation: 对DVB-S2标准中使用的诸如IRA代码的LDPC码进行解码的方法，包括具有度2的第一可变节点（系统），第二可变节点（奇偶校验）的代码图，以及通过Z字形连接到第二可变节点的校验节点 所述方法包括：a）将所述校验节点分组为至少一个组，每组的校验节点由称为内部变量节点的变量节点连接，b）对于每个组（GR i）执行以下子步骤b1） 和b2）：b1）通过使用两状态网格上的最大后验（MAP）类型的算法来共同更新（71）所述组的所有校验节点，b2）更新（72,73）所有 连接到除所述至少一个内部第二可变节点之外的所述组的第一可变节点和所有第二可变节点（PN i-1，i; PN i，i + 1），c）迭代地重复步骤b）当使用多个 组，相应的多个网格窗口是LogMAP解码而没有训练周期 根据sum-product算法更新连接奇偶校验节点。

公开(公告)号：EP2066056A1

公开(公告)日：2009-06-03

申请号：EP07121799.6

申请日：2007-11-28

Applicant: STMicroelectronics N.V.

Inventor： Berens, Friedbert ,  Derdiyok, Cem ,  Kienle, Frank ,  Lehnigk-Emden, Timo ,  Wehn, Norbert

IPC: H04L1/00

CPC classification number: H04L1/0057

Abstract: Method of decoding a received systematic code encoded block corresponding to an original block of information, said received encoded block (RENCB) including soft systematic values, said method comprising detecting (13) whether or not said received encoded block is considered in error, performing a decoding (15) of said received encoded block for retrieving said original block of information (BIF) if said received encoded block is considered in error, and processing only said soft systematic values (16) for retrieving said original block (BIF) of information if said received encoded block is not considered in error.

Abstract translation: 接收的系统码的编码块在信息原始块对应于解码的方法，所述接收的编码块（RENCB）包括软系统的值，所述方法包括：检测（13）所述接收的编码块是否被错误地考虑，在执行 说的解码（15）接收到用于如果检索的信息所述原始块（BIF）经编码块，用于检索的信息（BIF）所述原始块，如果所述接收到的编码块被错误地考虑，并且仅处理所述软系统的值（16） 所述接收到的编码块没有被错误地考虑。

公开(公告)号：EP1715589A1

公开(公告)日：2006-10-25

申请号：EP05290468.7

申请日：2005-03-02

Applicant: STMicroelectronics N.V.

Inventor： Wehn, Norbert ,  Kienle, Frank ,  Brack, Torben

IPC: H03M13/11

CPC classification number: H03M13/1165 ,  H03M13/1137 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6566

Abstract: The LDPC decoder (1) for decoding codewords, comprises processing means for updating messages exchanged iteratively between variable nodes (VN i ) and check nodes (CN i ) of a bipartite graph of said LDPC code. The decoder architecture is a partly parallel architecture clocked by a clock signal. The processing means comprises P processing units (PU i ). First variable nodes (IN i ) and check nodes (CN i ) are mapped on the P processing units (PU i ) according to two orthogonal directions. The decoder comprises P main memory banks (MMB i ) assigned to the P processing units (PU i ) for storing all the messages iteratively exchanged between said first variable nodes (IN i ) and the check nodes (CN i ). Each main memory bank (MMB i ) comprises at least two single port memory partitions (MP i ) and one buffer (BUF i ), the decoder also comprises a shuffling network (SN) and a shift memory (SM).

Abstract translation: 用于解码码字的LDPC解码器（1）包括用于更新在所述LDPC码的二分图的可变节点（VN i）和校验节点（CN i）之间迭代交换的消息的处理装置。 解码器架构是以时钟信号为时钟的部分并行架构。 处理装置包括P处理单元（PU i）。 根据两个正交方向，第一变量节点（IN i）和校验节点（CN i）被映射在P处理单元（PU i）上。 解码器包括分配给P处理单元（PU i）的P个主存储器组（MMB i），用于存储在所述第一可变节点（IN i）和校验节点（CN i）之间迭代交换的所有消息。 每个主存储器组（MMB i）包括至少两个单端口存储器分区（MP i）和一个缓冲器（BUF i），解码器还包括混洗网络（SN）和移位存储器（SM）。

公开(公告)号：EP2066056B1

公开(公告)日：2016-04-27

申请号：EP07121799.6

申请日：2007-11-28

Applicant: STMicroelectronics N.V.

Inventor： Berens, Friedbert ,  Derdiyok, Cem ,  Kienle, Frank ,  Lehnigk-Emden, Timo ,  Wehn, Norbert

IPC: H04L1/00

CPC classification number: H04L1/0057

公开(公告)号：EP1717959A1

公开(公告)日：2006-11-02

申请号：EP05009477.0

申请日：2005-04-29

Applicant: STMicroelectronics N.V.

Inventor： Wehn, Norbert ,  Kienle, Frank ,  Brack, Torben

IPC: H03M13/11 ,  H03M13/27 ,  H03M13/45

CPC classification number: H03M13/1111 ,  H03M13/1128 ,  H03M13/1165 ,  H03M13/3738

Abstract: This is a method for controlling the decoding of a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN i ) and variable nodes (VN i ). Said method comprises updating messages exchanged iteratively between variable nodes (VN i ) and check nodes (CN i ). Said method comprises, at each iteration, calculating for each variable node a first sum (Λ n ) of all the incident messages (λ i ) received by said variable node and the corresponding digital data (λ ch ) and calculating a second sum (VNR new ) of all the absolute values of the first sums (Λ n ), and stopping the decoding process if the second sum (VNR new ) is unchanged or decreases within two successive iterations and if a predetermined threshold condition is satisfied.

Abstract translation: 这是用于控制数个数字数据组成的LDPC编码码字的解码的方法，所述LDPC码由校验节点之间的二分图来表示（CN i）和变量节点（VN i）中。 所述方法包括迭代地更新变量节点（VN i）和校验节点（CN I）之间交换的消息。 所述方法包括，在每次迭代中，计算所有的事件消息（的每个变量节点的第一总和（> N）的“i）由所述变量节点接收，并且相应的数字数据（” CH）和计算第二总和（VNR 新）所述第一总和（> N）的所有绝对值，并停止解码过程中，如果所述第二总和（VNR新）不变或在两个连续的迭代，并且如果预定阈值条件满足减小。

公开(公告)号：EP1699138A1

公开(公告)日：2006-09-06

申请号：EP05290469.5

申请日：2005-03-02

Applicant: STMicroelectronics N.V.

Inventor： Wehn, Norbert ,  Kienle, Frank ,  Brack, Torben

IPC: H03M13/11 ,  H03M13/27

CPC classification number: H03M13/1165 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6563 ,  H03M13/6566

Abstract: The method for decoding a LDPC encoded codeword composed of several digital data, said LDPC code being represented by a bipartite graph between check nodes (CN i ) and variable nodes (VN i ) including first variable nodes (IN i ) and second variable nodes (PN i ) of degree 2 connected to the check nodes (CN i ) by a zigzag connectivity, comprises updating messages exchanged iteratively between variable nodes (VN i ) and check nodes (CN j ) including a first variable processing phase during which all the messages from the first variable nodes (IN i ) to the check nodes (CN i ) are updated and a check nodes processing phase during which all the messages from the check nodes (CN i ) to the first variable nodes (IN i ) are updated. Said check nodes processing phase further comprises updating all the messages from the second variable nodes (PN i ) to the check nodes (CN i ), and directly passing an updated message processed by a check node to the next check node through said zigzag connectivity.

Abstract translation: 数的数字数据构成的LDPC编码码字进行解码的方法，所述LDPC码由校验节点之间的二分图来表示（CN i）和变量节点（VN 1）包括第一变量节点（IN i）和第二个变量节点（ 度2的PN i）连接到校验节点（CN i）通过锯齿连接，包括更新（迭代的变量节点之间交换的消息VN i）和校验节点（CN j）​​的包含在此期间，所有的消息的第一可变处理相 从所述第一变量节点（IN i）与校验节点（CN i）的更新和校验节点处理阶段，在此期间所有来自校验节点的消息（CN i）至所述第一变量节点（IN i）的更新。 所述校验节点处理阶段还包括更新所有从第二变量节点（PN i）至校验节点的消息（CN i）中，并直接传递由校验节点处理，以通过所述Z字形连接的新的校验节点更新的消息。

公开(公告)号：EP1401108A1

公开(公告)日：2004-03-24

申请号：EP02292244.7

申请日：2002-09-12

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.A.

Inventor： Berens, Friedbert ,  Thul, Michael J. ,  Gilbert, Frank ,  Wehn, Norbert

IPC: H03M13/29 ,  H04L1/00

CPC classification number: H03M13/6566 ,  H03M13/2771

Abstract: The electronic device comprises a source memory means partitioned in N elementary source memories for storing a sequence of input data, processing means (MAP1) clocked by a clock signal and having N outputs for producing per cycle of the clock signal N data respectively associated to N input data respectively stored in the N elementary source memories at relative source addresses, N single port target memories (TMi), N interleaving tables (ILTi) containing for each relative source address the number of one target memory and the corresponding relative target address therein, N cells (CLi) connected in a ring structure, each cell being further connected between one output of the processing means, one interleaving table, and the port of one target memory, each cell being adapted to receive data from said output of the processing means and from its two neighbouring cells or to write at least some of these received data sequentially in the associated target memory, in accordance with the contents of said interleaving tables.

Abstract translation: 该电子设备包括一个源存储器装置在N个基本源存储器划分为每分别关联到N的时钟信号的N个数据的周期生产存储由时钟信号计时输入数据，处理装置（MAP 1）的序列，并且具有N个输出 分别在相对于源地址存储在所述N个基本源存储器的输入数据，N个单端口存储器目标（TMI），N交织表（ILTI）包含每个相对源地址一个目标存储器的数目和相应的相对的targetAddress其中， 连接成环的结构N个单元（CLI）中，每个小区被进一步地连接在所述处理装置的一个输出端，一个交织表，和一个目标存储器的端口，每个小区被angepasst从所述处理装置的所述输出接收数据之间 并从其两个相邻小区或写在相关联的目标存储器中的至少一些论文的接收到的数据顺序地，在雅舞的共 所述交织表ntents。