公开(公告)号：EP1542368A1

公开(公告)日：2005-06-15

申请号：EP03293074.5

申请日：2003-12-09

Applicant: STMicroelectronics N.V.

Inventor： Wellig, Armin ,  Zory, Julien

IPC: H03M13/27

CPC classification number: H03M13/2778 ,  H03M13/2707 ,  H03M13/276 ,  H04L1/0071

Abstract: The invention relates to de-interleaving successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows, in particular for high-throughput applications. The method comprises the steps of:

receiving each sequence of said interleaved data samples and writing row by row said received sequences of interleaved data samples in a de-interleaving memory array (2) having L rows and C columns, L being superior or equal to L0 and C being superior or equal to C0, and
de-interleaving the data samples stored in said de-interleaving memory array (2) sub-array by sub-array, the used predetermined sub-array being a square cluster array having a predetermined number SQ of rows and columns, the number L of rows and the number C of columns of the de-interleaving memory array (2) being multiples of the number SQ of rows and columns. De-interleaving the de-interleaving memory array (2) sub-array by sub-array allows to avoid memory re-use bottleneck and allows to decrease memory access rate.

Abstract translation: 本发明涉及一种去交错从具有C0，特别是用于高通量应用L0的列和行的虚拟存储器中提取交织后的数据样本的连续序列。 该方法包括以下步骤：接收所述交错数据样本的每个序列，并通过行写入行所述交错数据样本的接收序列中的去交织存储器阵列，具有L行和C列（2），L是大于或等于 L0和C是大于或等于C0，和去交织由子阵列存储在所述去交织存储器阵列（2）子阵列的数据样本，所使用的预定的子阵列是具有预定的正方形簇阵列 SQ数量的行和列，行的数目L和（2）是行数和列数的倍数SQ C中的解交织存储器阵列的列数。 解交织的解交织的存储器阵列（2）子阵列由子阵列允许避免存储器的再利用和瓶颈允许以降低存储器存取速率。

公开(公告)号：EP1555760B1

公开(公告)日：2008-05-28

申请号：EP04290135.5

申请日：2004-01-19

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.l.

Inventor： Zory, Julien ,  Speziali, Filippo

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/6566 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/3972

公开(公告)号：EP1564894B1

公开(公告)日：2011-01-12

申请号：EP04290424.3

申请日：2004-02-17

Applicant: STMicroelectronics N.V.

Inventor： Wellig, Armin ,  Zory, Julien

IPC: H03M13/39 ,  H03M13/45

CPC classification number: H03M13/451 ,  H03M13/13 ,  H03M13/23 ,  H03M13/3944

公开(公告)号：EP1564894A1

公开(公告)日：2005-08-17

申请号：EP04290424.3

申请日：2004-02-17

Applicant: STMicroelectronics N.V.

Inventor： Wellig, Armin ,  Zory, Julien

IPC: H03M13/39 ,  H03M13/45

CPC classification number: H03M13/451 ,  H03M13/13 ,  H03M13/23 ,  H03M13/3944

Abstract: Method for estimating a sequence of N bits (x̂ 0 x̂ 1 ...x̂ N-1 ) corresponding to a received sequence of M digital data (r 0 r 1 ...r M-1 ). The method comprising the steps of :

determining (31) candidate sequences of M RS digital data from a reduced reference sequence space comprising 2 N RS reduced reference sequences of M RS reference digital data (s 0 s 1 ...s M RS -1 ),M RS being inferior to M and 2 N RS being inferior or equal to 2 N ;
making up (32) each candidate sequence with remaining reference symbols to obtain at least one complete candidate sequence of M digital data ; and
determining (33) said sequence of N bits (x̂ 0 x̂ 1 ... x̂ N-1 ) from all the complete candidate sequences.

Abstract translation: 用于估计与接收的M个数字数据序列（r0r1 ... rM-1）相对应的N位序列（x / 0x / 1 ... x / N-1） 。 该方法包括以下步骤：从包括MRS参考数字数据（s0s1 ... sMRS-1）的2个NRS减少的参考序列的缩减参考序列空间中确定（31）MRS数字数据的候选序列，MRS低于 M和2 低于或等于2 ; 使用剩余的参考符号组成（32）每个候选序列，以获得M个数字数据的至少一个完整候选序列; 以及从所有完整的候选序列确定（33）所述N个比特序列（x / 0 x / 1 ... x / N-1）。

公开(公告)号：EP1542368B1

公开(公告)日：2008-07-30

申请号：EP03293074.5

申请日：2003-12-09

Applicant: STMicroelectronics N.V.

Inventor： Wellig, Armin ,  Zory, Julien

IPC: H03M13/27

CPC classification number: H03M13/2778 ,  H03M13/2707 ,  H03M13/276 ,  H04L1/0071

公开(公告)号：EP1555760A1

公开(公告)日：2005-07-20

申请号：EP04290135.5

申请日：2004-01-19

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.l.

Inventor： Zory, Julien ,  Speziali, Filippo

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/6566 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/3972

Abstract: A method and device for handling write access conflicts in interleaving, in particular for high-throughput turbo decoding for wireless communication systems; the device comprises N interleaving buffers (CLk) that are respectively connected to N producers (PRk), an LLR distributor means and N single port target memories (TMk). At any time step, each interleaving buffer receives m LLR inputs from the producers and has to write up to M of these into a register bank (RBk), which comprises W registers. M denotes the maximum number of concurrent write operations supported per time step and W denotes the maximum buffer size. M and W are design parameters and are chosen for the standard case and not for the worst case. m-M producers have to be stalled whenever m is larger than M and m producers have to be stalled whenever a buffer overflow occurs (more than W LLR values). Finally, at any time step one LLR value is fetched from the register bank and written to the SRAM interleaving memory.

Abstract translation: 一种用于处理交织中的写访问冲突的方法和装置，特别是用于无线通信系统的高吞吐量turbo解码; 该装置包括分别连接到N个生成器（PRk），LLR分配器装置和N个单端口目标存储器（TMk）的N个交织缓冲器（CLk）。 在任何时间步长中，每个交织缓冲器从生产者接收m个LLR输入，并且必须将这些M写入到包括W寄存器的寄存器组（RBk）中。 M表示每个时间步长支持的最大并发写操作数，W表示最大缓冲区大小。 M和W是设计参数，为标准情况选择，而不是最坏情况。 每当m大于M时，m-M生产者必须停顿，并且每当出现缓冲区溢出（多于W LLR值）时，生产者必须停止生产。 最后，在任何时候，从寄存器组中取出一个LLR值并将其写入SRAM交错存储器。

公开(公告)号：EP1633052A1

公开(公告)日：2006-03-08

申请号：EP04292140.3

申请日：2004-09-07

Applicant: STMicroelectronics N.V. ,  STMicroelectronics S.r.l.

Inventor： Wellig, Armin ,  Zory, Julien ,  Imbesi, Pasquale

IPC: H03M13/27

CPC classification number: H03M13/271 ,  H03M13/6566

Abstract: The block de-interleaving system comprises

input means for receiving a set of time-aligned blocks of interleaved data ;
physical memory means ; and
de-interleaving means for writing said blocks in said memory means in a first predetermined manner and reading said blocks from said memory means in a second predetermined manner in order to deinterleave the data of said blocks.

The physical memory means comprise several different physical elementary memories (M_1, M_2, ..., M_K), and by the fact that said de-interleaving means are adapted to totally write and read a block into and from one physical elementary memory (M_1, M_2, ..., M_K).

Abstract translation: 块解交织系统包括：输入装置，用于接收一组时间对准的交织数据块; 物理记忆手段; 以及去交错装置，用于以第一预定方式将所述块写入所述存储装置中，并以第二预定方式从所述存储装置中读取所述块，以便对所述块的数据去交错。 物理存储器装置包括若干不同的物理基本存储器（M_1，M_2，...，M_K），并且通过所述解交织装置适于将一个块完全写入一个物理基本存储器（M_1 ，M_2，...，M_K）。

公开(公告)号：EP1542369A1

公开(公告)日：2005-06-15

申请号：EP03293075.2

申请日：2003-12-09

Applicant: STMicroelectronics N.V.

Inventor： Wellig, Armin ,  Zory, Julien

IPC: H03M13/27

CPC classification number: H03M13/6505 ,  H03M13/2703 ,  H03M13/2792 ,  H03M13/2796

Abstract: Method of de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels (phc_0,phc_1,...,phc_S2-1) and able to be associated with S1 output transport channels (otc_0,otc_1,...,otc_S1-1). Said S2 received sequences have been delivered, before transmission, by a two-stages multi-interleaving device (2), from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels (itc_0,itc_1,...itc_S1-1). Said two-stages multi-interleaving device (2) comprises a first stage (3) including S1 interleaving blocks (Int1_0,Int1_1,...Int1_S1-1) respectively associated to the S1 initial transport channels (itc_0,itc_1,...itc_S1-1), a second stage (4) including S2 interleaving blocks (Int2_0,Int2_1,...Int2_S2-1) respectively associated to the S2 physical channels (phc_0,phc_1,...,phc_S2-1) and an inter-stage of predetermined data-routing functions (5) connected between said first and second stages (3,4). The two stages of interleavers (3,4) and the inter-stage of predetermined data routing functions (5) are merged into one stage and second and first stage de-interleaving is performed when the received data samples are written to memory elements (me_0,me_1,...me_S1-1) that are associated with the S1 output transport channels.

Abstract translation: 分别从S2物理信道（phc_0，phc_1，...，phc_S2-1）发出的能够与S1输出传输信道（otc_0，otc_1，...）相关联的交织的接收数据样本的接收序列的方法 ，otc_S1-1）。 所述S2接收的序列在传输之前由两级多重交织设备（2）从分别与S1初始传输信道（itc_0，itc_1，... itc_S1-1）相关联的有序数据样本的S1个初始序列传送 ）。 所述两级多交错装置（2）包括第一级（3），其包括分别与S1初始传输信道（itc_0，itc_1，...）分别相关联的S1交织块（Int1_0，Int1_1，... Int1_S1-1） itc_S1-1），包括分别与S2物理信道（phc_0，phc_1，...，phc_S2-1）相关联的S2交织块（Int2_0，Int2_1，... Int2_S2-1）的第二级（4） - 级连接在所述第一和第二级（3,4）之间的预定数据路由功能（5）。 交织器（3,4）的两个阶段和预定数据路由功能（5）的阶段被合并为一个阶段，并且当接收的数据样本被写入存储器元件（me_0）时，执行第二和第一阶段去交织 ，me_1，... me_S1-1），与S1输出传输通道相关联。