公开(公告)号：EP4227992A3

公开(公告)日：2023-12-06

申请号：EP23151738.4

申请日：2023-01-16

Applicant: STMicroelectronics Pte Ltd.

Inventor： CHEN, Yong ,  GANI, David

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.

公开(公告)号：EP3852139A3

公开(公告)日：2021-09-08

申请号：EP20215558.6

申请日：2020-12-18

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L23/485 ,  H01L21/60

Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) (100, 200, 300) with bumps with various combinations of conductive structures such as solder (118, 120, 214, 216, 314, 316) and under bump metallizations (UBMs) (112, 117, 311, 312) having different structures and different amounts of solder (118, 120, 214, 216, 314, 316) coupled to the UBMs (112, 117, 311, 312). Although the bumps have different structures and the volume (height) of solder (118, 120, 214, 216, 314, 316) differs, the total standoff height along the WLCSP (100, 200, 300) remains substantially the same. Each portion of solder (118, 120, 214, 216, 314, 316) includes a point furthest away from an active surface (103, 203, 303) of a die (102, 202, 302) of the WLCSP (100, 200, 300). Each point of each respective portion of solder (118, 120, 214, 216, 314, 316) is co-planar with each other respective point of the other respective portions of solder (118, 120, 214, 216, 314, 316). Additionally, the bumps with different structures are positioned accordingly on the active surface of the die (102, 202, 302) of the WLCSP (100, 200, 300) to reduce failures that may result from the WLCSP (100, 200, 300) being exposed to thermal cycling or the WLCSP (100, 200, 300) being dropped, or because of electromigration, in that less solder (118, 120, 214, 216, 314, 316) is used for bumps at corners of the WLCSP (100, 200, 300). The bumps with less solder comprise an additional contact structure (116, 212, 310) on which the solder (120, 214, 314) is formed. The bumps may be placed on a conductive redistribution layer (108, 208) or on contact pads (304) on the active surface (303) of the die (302) without a redistribution layer. During the manufacturing process, the conductive material (428) of the conductive structures (the solder) is filled in openings (424, 426) of a stencil (422), followed by removing excess portions of the conductive material (428) on the stencil (422) by a squeegee (430).

公开(公告)号：EP4362071A2

公开(公告)日：2024-05-01

申请号：EP23206096.2

申请日：2023-10-26

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L24/96 ,  H01L23/5389 ,  H01L23/3128 ,  H01L21/561 ,  H01L21/568

Abstract: The present disclosure is directed to at least one semiconductor package including a die (204) within an encapsulant (202) having a first sidewall, an adhesive layer (222) on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer (226) on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.

公开(公告)号：EP4227992A2

公开(公告)日：2023-08-16

申请号：EP23151738.4

申请日：2023-01-16

Applicant: STMicroelectronics Pte Ltd.

Inventor： CHEN, Yong ,  GANI, David

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/16

Abstract: A semiconductor package includes a die and a first lamination layer on the die with openings through the first lamination layer. A redistribution layer is on the first lamination layer and extends through the openings to the die. A plurality of conductive extensions are on the redistribution layer with each stud including a first surface on the redistribution layer, a second surface opposite to the first surface, and a sidewall between the first surface and the second surface. A second lamination layer is on the redistribution layer and the first lamination layer with the die encapsulated in molding compound. The second lamination layer is removed around the conductive extensions to expose the second surface and at least a portion of the sidewall of each stud to improve solder bond strength when mounting the package to a circuit board.

公开(公告)号：EP3923334A1

公开(公告)日：2021-12-15

申请号：EP21177013.6

申请日：2021-06-01

Applicant: STMicroelectronics Pte Ltd.

Inventor： HERARD, Laurent ,  GANI, David

IPC: H01L27/146

Abstract: Disclosed herein is a digital image sensor package including an image sensor substrate and a glass covering. The image sensor substrate carries photodiodes. The glass covering has a bottom surface, a top surface opposite the bottom surface, and a sidewall delimiting a perimeter edge of the glass covering. The glass covering overlies the photodiodes. A surface area of the top surface of the glass covering is greater than a surface area of the bottom surface of the glass covering such that the sidewall is anti-perpendicular to the top and bottom surfaces of the glass.

公开(公告)号：EP3852139A2

公开(公告)日：2021-07-21

申请号：EP20215558.6

申请日：2020-12-18

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L23/485 ,  H01L21/60

Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) (100, 200, 300) with bumps with various combinations of conductive structures such as solder (118, 120, 214, 216, 314, 316) and under bump metallizations (UBMs) (112, 117, 311, 312) having different structures and different amounts of solder (118, 120, 214, 216, 314, 316) coupled to the UBMs (112, 117, 311, 312). Although the bumps have different structures and the volume (height) of solder (118, 120, 214, 216, 314, 316) differs, the total standoff height along the WLCSP (100, 200, 300) remains substantially the same. Each portion of solder (118, 120, 214, 216, 314, 316) includes a point furthest away from an active surface (103, 203, 303) of a die (102, 202, 302) of the WLCSP (100, 200, 300). Each point of each respective portion of solder (118, 120, 214, 216, 314, 316) is co-planar with each other respective point of the other respective portions of solder (118, 120, 214, 216, 314, 316). Additionally, the bumps with different structures are positioned accordingly on the active surface of the die (102, 202, 302) of the WLCSP (100, 200, 300) to reduce failures that may result from the WLCSP (100, 200, 300) being exposed to thermal cycling or the WLCSP (100, 200, 300) being dropped, or because of electromigration, in that less solder (118, 120, 214, 216, 314, 316) is used for bumps at corners of the WLCSP (100, 200, 300). The bumps with less solder comprise an additional contact structure (116, 212, 310) on which the solder (120, 214, 314) is formed. The bumps may be placed on a conductive redistribution layer (108, 208) or on contact pads (304) on the active surface (303) of the die (302) without a redistribution layer. During the manufacturing process, the conductive material (428) of the conductive structures (the solder) is filled in openings (424, 426) of a stencil (422), followed by removing excess portions of the conductive material (428) on the stencil (422) by a squeegee (430).

公开(公告)号：EP4362071A3

公开(公告)日：2024-09-25

申请号：EP23206096.2

申请日：2023-10-26

Applicant: STMicroelectronics Pte Ltd.

Inventor： GANI, David

IPC: H01L21/60 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L23/5389 ,  H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L24/97 ,  H01L21/6835 ,  H01L2221/6834520130101

Abstract: The present disclosure is directed to at least one semiconductor package including a die (204) within an encapsulant (202) having a first sidewall, an adhesive layer (222) on the encapsulant and having a second sidewall coplanar with the first sidewall of the encapsulant, and an insulating layer (226) on the adhesive layer having a third sidewall coplanar with the first sidewall and the second sidewall. A method of manufacturing the at least one semiconductor package includes forming an insulating layer on a temporary adhesion layer of a carrier, forming an adhesive layer on the insulating layer, and forming a plurality of openings through the adhesive layer and the insulating layer. The plurality of openings through the adhesive layer and the insulating layer may be formed by exposing the adhesive layer and the insulating layer to a laser.