公开(公告)号：EP1411431A2

公开(公告)日：2004-04-21

申请号：EP03020154.5

申请日：2003-09-05

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, Ashish Kumar ,  Khanna, Namerita ,  Aggarwal, Davinder

IPC: G06F11/14

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: The invention provides an improved method and apparatus for reloading only those frames in which errors are detected during the FPGA configuration. A configuration data frame for a FPGA is sumultaneously loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value 'n'. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and recheked for errors. If no error os detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一个新的配置数据帧被加载到帧寄存器和误差检测电路（700）。 在数据帧中的错误进行检查，并且如果没有检测到错误的数据的可编程逻辑器件存储器锁存器的传输被执行。 帧寄存器重新加载和错误计数器（706）的值被递增，如果遇到错误。 因此独立claimsoft包含用于可编程逻辑器件。

公开(公告)号：EP1521187A1

公开(公告)日：2005-04-06

申请号：EP04104798.6

申请日：2004-09-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Goel, Ashish Kumar ,  Aggarwal, Davinder

IPC: G06F17/50 ,  H03K19/177

CPC classification number: H03K19/17748 ,  G06F17/5054 ,  H03K19/1776

Abstract: The present invention relates to a Programmable Logic Device providing efficient scalability for configuration memory programming while requiring reduced area for implementation, comprising: an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.

Abstract translation: 本发明涉及一种可编程逻辑器件，其为配置存储器编程提供有效的可扩展性，同时需要减少实现的面积，其包括：配置存储器单元的阵列，连接到配置存储器阵列的垂直线的垂直移位寄存器（VSR） 单元，连接到配置存储单元阵列的水平线的选择寄存器（SR），提供对选择寄存器（SR）的使能输入的水平移位寄存器（HSR）以及同步的配置状态机（CSM） VSR，SR和HSR的操作。