公开(公告)号：EP1650869A1

公开(公告)日：2006-04-26

申请号：EP05109736.8

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bhuvanagiri, Aditya ,  Malik, Rakesh ,  Chawla, Nitin

IPC: H03H17/02 ,  G06F7/00 ,  G06F17/50

CPC classification number: H03H17/0225

Abstract: The present invention provides a device for implementing a sum-of-products expression comprising a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/ complex sum-of -products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from said 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein , a third set of 2SAD blocks receiving recursively and vertically optimized response from said first set of 2SAD block and said second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from said blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from said fourth set of 2SAD blocks, for generating the final output.

Abstract translation: 本发明提供了一种用于实现产品总和表达式的装置，包括：第一组2-输入移位和加法（2SAD）块，其接收用于产生第一组的第一组的系数组/复数和和积表达式 通过在其中应用递归优化来实现部分优化的表达项;第二组1-输入移位和加法（1SAD）块，其从所述2SAD块接收响应，用于通过在其中应用垂直优化来产生第二组部分优化表达项，第三组 一组2SAD块从所述第一组2SAD块和所述第二组1SAD块接收递归和垂直优化的响应，用于通过在其中应用水平优化来产生第三组部分优化的表达项，第四组2SAD块从所述 用于通过应用分解和因式分解来产生第四组部分优化的表达式的块，以及第五组2SAD块 接收来自所述第四组2SAD块的响应，用于产生最终输出。