公开(公告)号：EP1653747A2

公开(公告)日：2006-05-03

申请号：EP05022773.5

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kaushik, Saha ,  Chakraborty, Chiranjib ,  Chatterjee, Subrata

IPC: H04N7/62

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.

Abstract translation: 一种用于数字视频通信中的时钟恢复的系统，包括用于产生PCR输入信号的延迟测量块和用于连续地确定连续的PCR输入信号之间的时间间隔的第一存储装置，用于产生对应于连续到达之间的所述时间间隔的第一PCR信号 PCR输入信号，PCR到达间时间计算滤波装置，用于确定连续PCR分组之间的平均到达时差。 一种用于最小化连续PCR分组之间的平均PCR差异误差的纠错装置，连接到所述纠错装置的输出以产生系统时钟的受控系统时钟发生器，用于产生第一系统时钟输出的第二存储装置， 控制时钟周期差计算元件，用于计算所述第一和第二系统时钟输出之间的时钟周期差，并且所述受控时钟周期差计算元件在其输出处耦合到所述纠错装置，以形成反馈电路，以使所述第一和第二系统时钟输出之间的误差最小化 观察系统时钟输出和连续的PCR差异。

公开(公告)号：EP1653747A3

公开(公告)日：2009-06-17

申请号：EP05022773.5

申请日：2005-10-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Kaushik, Saha ,  Chakraborty, Chiranjib ,  Chatterjee, Subrata

IPC: H04N7/62

CPC classification number: H04N21/4305

Abstract: A system for clock recovery in digital video communication comprising a delay measurement block for generating PCR input signals and for continuously determining time interval between successive PCR input signals, a first storage device for generating a first PCR signal corresponding to said time interval between arrival of successive PCR input signals, a PCR inter-arrival time computation filtering device for determining the average time of arrival difference between successive PCR packets. An error correction device for minimizing the error in the average PCR difference between successive PCR packets, a controlled system clock generator connected to the output of said error correction device to generate system clock, a second storage device for generating a first system clock output, a controlled clock period difference computation element for computing the clock period difference between said first and second system clock output, and said controlled clock period difference computation element is coupled at its output to said error correction device to form a feedback circuit for minimizing the error between said system clock output and successive PCR differences observed.