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公开(公告)号：EP1653331A3
公开(公告)日：2009-09-16
申请号：EP05110131.9
申请日：2005-10-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： DHIMAN, Gaurav , KAPOOR, Gaurav
CPC classification number: G06F1/30 , G06F1/3203 , G06F9/4418
Abstract: An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a prefetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said prefetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.
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公开(公告)号：EP1653331A2
公开(公告)日：2006-05-03
申请号：EP05110131.9
申请日：2005-10-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： DHIMAN, Gaurav , KAPOOR, Gaurav
CPC classification number: G06F1/30 , G06F1/3203 , G06F9/4418
Abstract: An apparatus for entering and exiting low power mode comprising a processor having a cache; a power management mechanism connected to said processor for controlling a plurality of power management states, at least one of said power management states being a low latency low power state; a memory subsystem including a self sustaining mechanism connected to said processor for retaining data during said low power state; a prefetching means in said memory subsystem for loading instructions into a cache prior to entering said low power state; a disabling mechanism in said processor for disabling any interrupts that may disturb said prefetched instructions; an enabling means in said memory subsystem for initiating the self sustaining operation of said memory subsystem; a detecting means connected to said processor for sensing a trigger to exit from said low power state; and a restoring means in said power management mechanism for restoring the clock of said apparatus; thereby said processor disabling said self sustaining operation and resuming normal operation at the end of said low power state.
Abstract translation: 对于进入和退出低功率模式，其包括具有高速缓存的处理器的装置; 连接到所述处理器，用于控制电源管理状态，所述电源管理状态是低等待时间低功率状态中的至少一个的多个电源管理机制; 存储器子系统包括连接到所述处理器，用于所述低功率状态期间保持的数据的自我维持机构; 预取在用于加载指令到高速缓存所述存储器子系统进入所述低功率状态之前，装置; 一个禁用在所述处理器机制，用于禁止任何中断都可能干扰。所述预取指令; 在所述存储器子系统使能装置，用于启动自维持存储器子系统的操作。所述; 检测连接到所述处理器，用于感测触发从所述低功率状态退出的装置; 和恢复在所述电源管理机制用于恢复所述设备的时钟; 由此，所述处理器禁用所述自持运行，并在所述低功率状态的结束恢复正常运作。
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公开(公告)号：EP1653331B1
公开(公告)日：2011-09-21
申请号：EP05110131.9
申请日：2005-10-28
Applicant: STMicroelectronics Pvt. Ltd.
Inventor： DHIMAN, Gaurav , KAPOOR, Gaurav
CPC classification number: G06F1/30 , G06F1/3203 , G06F9/4418
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