公开(公告)号：EP1330033A2

公开(公告)日：2003-07-23

申请号：EP03000105.1

申请日：2003-01-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chauhan, Rajat ,  Kaushik, Rajesh

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 本发明提供一种方法和改善的FPGA装置用于使得未使用的触发器或在IO单元和未使用的解码器或在查找表（LUT），用于核心逻辑功能的其它电路元件的其它电路元件的选择性地部署，包括断开装置 选择性地断开所述IO垫的电路或从所述LUT电路未使用的电路元件和连接装置，用于所述断开电路元件选择性地连接到要么核心逻辑的连接基质或在它们之间，以提供unabhängig配置的功能。

公开(公告)号：EP1330033A3

公开(公告)日：2006-11-29

申请号：EP03000105.1

申请日：2003-01-02

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chauhan, Rajat ,  Kaushik, Rajesh

IPC: H03K19/177

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: This invention provides a method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.