公开(公告)号：EP1359588A2

公开(公告)日：2003-11-05

申请号：EP03009612.7

申请日：2003-04-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: G11C8/14

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

Abstract translation: 一种改进的多字线存储器架构，其提供降低的位线耦合以提高速度和降低的功耗，包括用于将相邻位单元连接到不同字线的交错布置，耦合到用于共享相邻位单元的位线的复用布置。

公开(公告)号：EP1443650A3

公开(公告)日：2006-11-15

申请号：EP04001539.8

申请日：2004-01-26

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: H03K19/00

CPC classification number: G11C5/063 ,  H03K19/0019

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source / sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source / sink during an idle period prior to a change of state.
This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary line.

公开(公告)号：EP1359588A3

公开(公告)日：2005-11-30

申请号：EP03009612.7

申请日：2003-04-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: G11C8/14 ,  G11C7/18

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: An improved multi-wordline memory architecture providing decreased bitline coupling for increased speed and reduced power consumption comprising an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

公开(公告)号：EP1443650A2

公开(公告)日：2004-08-04

申请号：EP04001539.8

申请日：2004-01-26

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Nautiyal, Vivek ,  Kumar, Ashish

IPC: H03K19/00

CPC classification number: G11C5/063 ,  H03K19/0019

Abstract: A method and system for reducing power consumption in digital circuits using charge redistribution, comprising a plurality of signal lines, an intermediate floating virtual source / sink, and a charge redistribution circuit connected to each said signal line that isolates said line from its source and connects it to the intermediate floating virtual source / sink during an idle period prior to a change of state.
This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary line.

Abstract translation: 一种用于使用电荷再分配减少数字电路的功耗，包括的信号线。多个中间浮动虚源/汇的方法和系统，以及连接到每个所述信号线的电荷重新分布电路的确从它的源和所连接隔离所述线 它的中间浮动虚源/在状态变化之前，空闲期间下沉。 这种电荷再分配提供由于电荷循环不插入额外的免费在线稳态统计独立的优势。