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公开(公告)号：EP1505732A1
公开(公告)日：2005-02-09
申请号：EP04103610.4
申请日：2004-07-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： NANDY, Tapas
CPC classification number: H03K5/133 , H03K5/1252 , H04B15/04 , H04B2215/064 , H04B2215/067
Abstract: The present invention provides a digital clock modulator providing a smoothly modulated clock period to reduce emitted Electro-Magnetic Radiation (EMR) comprising a plurality of delay elements (14) connected in series receiving an unmodulated clock signal at the input, connected to a multiplexer (11) receiving inputs from unequally spaced selected taps provided between the delay elements. A control block (12) supplies the selection-inputs to said multiplexer (11), and receives a clock signal from said series of delay elements. Further, a predetermined delay element (13) is connected between the clock terminal of the said control block (12) and the last element U(n) of said series of delay elements for enabling glitch free operation by ensuring that the entire delay chain and related signal paths are in the same stable state before the control to the multiplexer changes.
Abstract translation: 本发明提供了一种数字时钟调制器，其提供平滑调制的时钟周期以减少发射的电磁辐射（EMR），其包括多个延迟元件（14），所述多个延迟元件（14）串联接收连接到多路复用器的输入处的未调制时钟信号 11）从延迟元件之间提供的不等间隔的选择的抽头接收输入。 控制块（12）将选择输入提供给所述多路复用器（11），并且从所述一系列延迟元件接收时钟信号。 此外，预定的延迟元件（13）连接在所述控制块（12）的时钟端子和所述一系列延迟元件的最后一个元件U（n）之间，以便通过确保整个延迟链和 在对多路复用器的控制变化之前，相关的信号路径处于相同的稳定状态。
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公开(公告)号：EP1505732B1
公开(公告)日：2007-09-26
申请号：EP04103610.4
申请日：2004-07-28
Applicant: STMicroelectronics Pvt. Ltd
Inventor： NANDY, Tapas
CPC classification number: H03K5/133 , H03K5/1252 , H04B15/04 , H04B2215/064 , H04B2215/067
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