公开(公告)号：EP1460640A3

公开(公告)日：2005-05-04

申请号：EP04006654.0

申请日：2004-03-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Srivastavaan, Rajeev ,  Grover, Chiranjeev

IPC: G11C15/04

CPC classification number: G11C15/00

Abstract: This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.

公开(公告)号：EP1460640A2

公开(公告)日：2004-09-22

申请号：EP04006654.0

申请日：2004-03-19

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Srivastavaan, Rajeev ,  Grover, Chiranjeev

IPC: G11C15/04

CPC classification number: G11C15/00

Abstract: This invention provides a Content Addressable Memory (CAM) architecture providing improved speed by performing mutually exclusive operations in a first state of a clock cycle and by performing at least one operation, dependent on at least one previous operations, in a second state of the same clock cycles. The Content Addressable Memory (CAM) architecture (300) comprises an array of CAM cells (303) connected to a compare-data-write-driver (302) and to a read/write block (305), for receiving a compare-data and for reading and/or writing data in the array of CAM cells (303) respectively, outputs of the said CAM cells of said array (303) are coupled to a match block (304) providing match outputs signal lines that identifies a match/no-match at the end of a search operation, and a control logic for implementing search and address decoding operations during a first state and enabling read-or-write operations within a second state of the same clock cycle in the event of a match.

Abstract translation: 本发明提供了一种内容寻址存储器（CAM）架构，其通过在时钟周期的第一状态中执行互斥操作并且依赖于至少一个先前的操作在相同的第二状态中执行至少一个操作来提供改进的速度 时钟周期。 内容可寻址存储器（CAM）架构（300）包括连接到比较数据写驱动器（302）和读/写块（305）的CAM单元阵列（303），用于接收比较数据 并且分别用于在CAM单元阵列中读取和/或写入数据，所述阵列（303）的所述CAM单元的输出耦合到匹配块（304），提供匹配输出信号线，其标识匹配/ 在搜索操作结束时的不匹配，以及用于在第一状态下实现搜索和地址解码操作以及在匹配的情况下在相同时钟周期的第二状态内启用读或写操作的控制逻辑。