Abstract:
A glitch free controlled ring oscillator comprising a programmable delay chain (1) connected to a gating and inverting means (3) wherein a latching means (2) is provided between said prgrammable delay chain (1) and said gating and inverting means (3) for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.
Abstract:
A glitch free controlled ring oscillator comprising a programmable delay chain connected to a gating and inverting means wherein a latching means is provided between said delay chain and said gating and inverting means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.