公开(公告)号：EP1432126A2

公开(公告)日：2004-06-23

申请号：EP03104727.7

申请日：2003-12-16

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： BAL, Ankur ,  KHANNA, Namerita

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.

Abstract translation: 描述了一种高性能互连架构，其提供减少的延迟最小化电迁移和FPGA中的减小的区域，包括由互连的逻辑块组成的多个瓦片，其由中间的逻辑块分隔。 每组相互连接的逻辑块通过互连段链接，所述互连段通过互连层穿过中间逻辑块以直线布线，并且通过连接段选择性地连接到逻辑块。

公开(公告)号：EP1432126A3

公开(公告)日：2006-06-14

申请号：EP03104727.7

申请日：2003-12-16

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： BAL, Ankur ,  KHANNA, Namerita

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

Abstract: A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.