公开(公告)号：EP1811370A2

公开(公告)日：2007-07-25

申请号：EP06027048.5

申请日：2006-12-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kapil, Batra

IPC: G06F5/06 ,  G06F5/16

CPC classification number: G06F5/065 ,  G06F5/16 ,  G11C7/1075

Abstract: The present invention related to a first-in first-out (FIFO) memory architecture (10, 20) providing multiport functionality and comprising:
- a plurality of single-port memory structures (11, 21a, 21b);
- an indexing block (12, 22) for storing information about a single-port memory structure (11, 21a, 21b) in which incoming data is being stored in each data write operation; and
- an access controller (13, 23) for controlling operations on the single-port memory structures (11, 21a, 21b) based on the contents of the indexing block (12, 22).
A method of operating a plurality of single port memory structures (11, 21a, 21b) as a FIFO multiport memory architecture (10, 20) for sequential memory operations is also described.

Abstract translation: 本发明涉及提供多端口功能的先进先出（FIFO）存储器架构（10,20），并且包括： - 多个单端口存储器结构（11,21a，21b）; - 索引块（12,22），用于存储关于在每个数据写入操作中存储输入数据的单端口存储器结构（11,21a，21b）的信息; 以及 - 用于基于所述分度块（12,22）的内容来控制对所述单端口存储器结构（11,21a，21b）的操作的访问控制器（13,23）。 还描述了操作用于顺序存储器操作的多个单端口存储器结构（11,21a，21b）作为FIFO多端口存储器架构（10,20）的方法。