公开(公告)号：EP1811664A3

公开(公告)日：2010-01-27

申请号：EP06127217.5

申请日：2006-12-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sen, Tanmoy ,  Kumar, Anand ,  Kumar Jain, Deependra Padam Chand Jain

IPC: H03K5/15

CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/15013 ,  H03K5/15026 ,  H03K5/1506 ,  H03K2005/00241 ,  H03K2005/00247 ,  H03L7/095 ,  H03L7/0995 ,  Y10S331/02

Abstract: A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (401) (VCO) and multiple clock dividers (402A-402M). The voltage controlled oscillator (VCO) is made to operate at frequency 'N' times higher than the required output frequency. It generates 'M' equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of 'M x N' equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic (403) is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output. This maintains the sequence of the output of the Johnson counters.

公开(公告)号：EP1811664A2

公开(公告)日：2007-07-25

申请号：EP06127217.5

申请日：2006-12-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sen, Tanmoy ,  Kumar, Anand ,  Kumar Jain, Deependra Padam Chand Jain

IPC: H03K5/15

CPC classification number: H03K3/0315 ,  H03K3/03 ,  H03K5/15013 ,  H03K5/15026 ,  H03K5/1506 ,  H03K2005/00241 ,  H03K2005/00247 ,  H03L7/095 ,  H03L7/0995 ,  Y10S331/02

Abstract: A system and method for multiple phase clock generation is disclosed. The disclosed multiple phase clock circuit comprises of a multiple stage voltage controlled oscillator (401) (VCO) and multiple clock dividers (402A-402M). The voltage controlled oscillator (VCO) is made to operate at frequency 'N' times higher than the required output frequency. It generates 'M' equally spaced outputs having different phases but same frequency which are sent to multiple clock dividers. A modified Johnson counter is used as a clock divider. Each counter divides the frequency of the clock signal by N. As a result, each of the M outputs of the VCO are divided into N outputs, thereby making a total of 'M x N' equally spaced outputs. These output clock pulses have same frequency but different phases. A sequential logic (403) is provided within the device for enabling the Johnson counters as soon as the VCO starts giving output. This maintains the sequence of the output of the Johnson counters.

Abstract translation: 公开了一种用于多相时钟产生的系统和方法。 所公开的多相时钟电路包括多级压控振荡器（401）（VCO）和多个时钟分频器（402A-402M）。 压控振荡器（VCO）的工作频率高于所需输出频率的“N”倍。 它产生具有不同相位但相同频率的“M”等间距输出，发送到多个时钟分频器。 修改后的约翰逊计数器用作时钟分频器。 每个计数器将时钟信号的频率除以N.结果，VCO的M个输出中的每一个被分成N个输出，从而形成总共“M×N”个等间隔的输出。 这些输出时钟脉冲具有相同的频率但不同的相位。 一旦在VCO开始输出时，该器件内就提供一个顺序逻辑（403），用于启用约翰逊计数器。 这保持了约翰逊计数器的输出顺序。