公开(公告)号：EP1443645B1

公开(公告)日：2010-01-06

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

公开(公告)号：EP1443645A3

公开(公告)日：2004-09-15

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

公开(公告)号：EP1443645A2

公开(公告)日：2004-08-04

申请号：EP03104135.3

申请日：2003-11-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： SAHA, Kaushik ,  MAITI, Srijib Narayan

IPC: H03H17/06

CPC classification number: H03H17/0223 ,  H03H17/06 ,  H03H2017/0298

Abstract: The present invention provides an improved Finite Impulse Response (FIR) filter providing linear scalability and implementation without the need for delay lines, comprising a multiprocessor architecture including a plurality of ALUs (Arithmetic and Logic Units), multipliers units, data cache, and load/store units sharing a common instruction cache, and multi-port memory, and an assigning means for assigning to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values. A method is also provided for implementing an improved Finite Impulse Response (FIR) filter providing linear scalability using a multiprocessing architecture platform without the need for delay lines.

Abstract translation: 本发明提供了一种改进的有限脉冲响应（FIR）滤波器，其提供线性可扩展性和实现，而不需要延迟线，包括包括多个ALU（算术和逻辑单元），乘法器单元，数据高速缓存和负载/ 共享公共指令高速缓存的存储单元和多端口存储器，以及分配装置，用于向每个可用处理单元分配指定的唯一部分乘积项的计算以及每个计算的部分乘积在指定的输出样本值上的累积。 还提供了一种用于实现改进的有限脉冲响应（FIR）滤波器的方法，其使用多处理架构平台提供线性可扩展性，而不需要延迟线。