公开(公告)号：WO2007006764A2

公开(公告)日：2007-01-18

申请号：PCT/EP2006/064035

申请日：2006-07-07

Applicant: STMICROELECTRONICS S.r.l. ,  ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

Inventor： ARENA, Giuseppe ,  DONATO, Caterina ,  CAMALLERI, Cateno Marco ,  MAGRI', Angelo

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/66734

Abstract: A trench (5) is formed in a semiconductor body (2); the side walls and the bottom of the trench are covered with a first dielectric material layer (9); the trench (5) is filled with a second dielectric material layer (10); the first and the second dielectric material layers (9, 10) are etched via a partial, simultaneous and controlled etching such that the dielectric materials have similar etching rates; a gate-oxide layer (13) having a thickness smaller than the first dielectric material layer (9) is deposited on the walls of the trench (5); a gate region (14) of conductive material is formed within the trench (5); and body regions (7) and source regions (8) are formed within the semiconductor body (2), at the sides of and insulated from the gate region (14). Thereby, the gate region (14) extends only on top of the remaining portions of the first and second dielectric material layers (9, 10).

Abstract translation: 沟槽（5）形成在半导体本体（2）中; 沟槽的侧壁和底部被第一介电材料层（9）覆盖; 沟槽（5）填充有第二电介质层（10）; 通过部分，同时和受控的蚀刻蚀刻第一和第二介电材料层（9,10），使得介电材料具有相似的蚀刻速率; 在沟槽（5）的壁上沉积具有小于第一介电材料层（9）的厚度的栅极 - 氧化物层（13）。 在沟槽（5）内形成导电材料的栅区（14）; 并且在半导体本体（2）中，在栅极区域（14）的侧面和与栅极区域（14）绝缘的位置上形成有主体区域（7）和源极区域（8）。 因此，栅极区域（14）仅在第一和第二介电材料层（9,10）的剩余部分的顶部延伸。

公开(公告)号：WO2012020290A3

公开(公告)日：2012-02-16

申请号：PCT/IB2011/001724

申请日：2011-07-26

Applicant: STMICROELECTRONICS S.R.L. ,  SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

Inventor： SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

IPC: H01L21/20 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: A process for manufacturing a semiconductor device (10; 10') envisages the steps of: providing a semiconductor material body (2) having at least one deep trench (4) that extends through said body of semiconductor material starting from a top surface (2a) thereof; and filling the deep trench (4) via an epitaxial growth of semiconductor material, thereby forming a columnar structure (8) within the body of semiconductor material (2). The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench (4); in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.

公开(公告)号：EP2599107B1

公开(公告)日：2016-12-21

申请号：EP11810872.9

申请日：2011-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

IPC: H01L21/20 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3247 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench; in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.

公开(公告)号：EP2599107A2

公开(公告)日：2013-06-05

申请号：EP11810872.9

申请日：2011-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario, Giuseppe ,  MURABITO, Domenico ,  FIORE, Letterio ,  MORALE, Giuseppe ,  ARENA, Giuseppe

IPC: H01L21/20 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/762 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3247 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A process for manufacturing a semiconductor device envisages the steps of: providing a semiconductor material body having at least one deep trench that extends through said body of semiconductor material starting from a top surface thereof; and filling the deep trench via an epitaxial growth of semiconductor material, thereby forming a columnar structure within the body of semiconductor material. The manufacturing process further envisages the step of modulating the epitaxial growth by means of a concurrent chemical etching of the semiconductor material that is undergoing epitaxial growth so as to obtain a compact filling free from voids of the deep trench; in particular, a flow of etching gas is introduced into the same reaction environment as that of the epitaxial growth, wherein a flow of source gas is supplied for the same epitaxial growth.