公开(公告)号：EP4099368A1

公开(公告)日：2022-12-07

申请号：EP22175662.0

申请日：2022-05-26

Applicant: STMicroelectronics S.r.l.

Inventor： TIZIANI, Roberto ,  BELIZZI, Antonio

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495

Abstract: A method of manufacturing semiconductor devices (100), such as "die pad up" QFN (Quad-Flat No-lead) packages, comprises arranging a plurality of semiconductor chips (C) on an elongated substrate (10) and providing an insulating encapsulation (12) of the semiconductor chips (C). Electrically conductive formations (14) are plated on the insulating encapsulation (12). This may comprise Laser Direct Structuring, LDS or Direct Copper Interconnect, DCI material. Plating may include forming electrically conductive plating lines, the plating lines comprising first transverse plating lines as well as second plating lines 142 branching out from the first plating lines the towards the electrically conductive formations. A first partial cutting step removes the first plating lines extending transversely thus replacing them with grooves into which insulating material (18) is dispensed to encapsulate the end portions (142a) of the second plating lines (142). A second cutting step (B2) through the elongate substrate (10) having the semiconductor chips (C) arranged thereon and the insulating encapsulation (12) produces singulated semiconductor devices wherein the end portions (142a) of the second plating lines (142) are encapsulated by the insulating material (18).