公开(公告)号：EP4443265A1

公开(公告)日：2024-10-09

申请号：EP24164192.7

申请日：2024-03-18

Applicant: STMicroelectronics S.r.l.

Inventor： BIMBI, Cesare ,  PRIVITERA, Salvatore Giuseppe ,  PULVIRENTI, Francesco

IPC: G05F3/24 ,  G05F1/575

CPC classification number: G05F3/24 ,  G05F1/575

Abstract: A voltage regulation circuit (20;20';60) receiving as input an input voltage (VCC), in particular a DC voltage supply, and outputting a regulated voltage (VREG),
comprising a voltage reference circuit (50;90) configured to supply a reference voltage (VREF) which is independent, in particular with respect to temperature variations
said voltage regulation circuit (20;20';60) comprising a first circuit branch (B1) and a second circuit branch (B2) in parallel coupled between said input voltage (VCC) and ground (GND),
said first branch (B1) comprising
a current generator (31; 71) comprising a first depletion MOSFET transistor (QD2), which gate source voltage is a PTAT (Proportional To Absolute Temperature) voltage, coupled between said input voltage (VCC) and the voltage reference circuit (50;90),
said voltage reference circuit (50;90) comprising a first enhancement MOSFET transistor (QE2), which gate source voltage is a CTAT (Complementary To Absolute Temperature) voltage, coupled to the ground (GND) by its source through a source resistor (R5), on which a reference voltage (VREF), sum of the PTAT voltage drop (VP) on the source resistor (R5) and of the gate source voltage (VGS(QE2)) of the enhancement MOSFET transistor (QE2) being formed, said first enhancement MOSFET transistor (QE2) being arranged on said first branch (B1) and coupled by the drain to said first depletion MOSFET transistor (QD2) in a control node (C), said control node (C) being coupled to the gate of said first enhancement MOSFET transistor (QE2),
said first depletion MOSFET transistor (QD2) injecting a PTAT current (ID2) in said first branch (B1) determining a PTAT voltage drop (VP) on said source resistor (R5),
said second branch (B2) comprising an output stage (33; 73) coupled between said voltage to regulate (VCC) and an output node (REG) on which said regulated voltage (VREG) is taken, said output stage (33) comprising a second depletion MOSFET transistor (QD4) on which output is taken said output node (REG), a resistive voltage divider (40; 80) being coupled to said output node (REG), outputting on a respective divider output node (A) a divided output regulated voltage (VREG) which is inputted as the process variable of a negative feedback loop (QE2; 75) which is also coupled to said reference voltage (VREF), the output of said negative feedback loop (QE2; 75) controlling the gate of said second MOSFET transistor (QD4).