Method for testing a CMOS integrated circuit
    1.
    发明授权
    Method for testing a CMOS integrated circuit 有权
    测试的CMOS集成电路的方法

    公开(公告)号:EP1118867B1

    公开(公告)日:2005-10-19

    申请号:EP00830021.2

    申请日:2000-01-18

    CPC classification number: G01R31/3004 G01R31/3008

    Abstract: A CMOS integrated circuit is tested with the following steps: establishing a current threshold value (Ith), power the integrated circuit in static and idle conditions, measuring the current absorbed (IDDQ) by the integrated circuit and comparing this with the threshold value (Ith) and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured (IDDQ) is respectively lower or higher than the threshold value (Ith). To improve discrimination between sound and faulty devices, the threshold value (Ith) is obtained from the following steps: forming two measurement transistors (Mn, Mp) in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents (Isubn, Isubp), calculating the sub-threshold currents by channel unit of area of the transistors of the integrated circuit using the sub-threshold currents measured (Isubn, Isubp) and the channel areas of the measurement transistors (Mn, Mp), obtaining the sum of the channel areas of the transistors that are cut off when the integrated circuit is idle in static conditions, calculating the current absorbed by the integrated circuit when idle in static conditions (IDDQ) using the result of the two operations described above and adding a pre-established current increase DELTA I to the current absorbed (IDDQ) in order to obtain the threshold value (Ith).

    Method for testing a CMOS integrated circuit
    2.
    发明公开
    Method for testing a CMOS integrated circuit 有权
    Verfahren zurPrüfungeiner CMOS integrierten Schaltungen

    公开(公告)号:EP1118867A1

    公开(公告)日:2001-07-25

    申请号:EP00830021.2

    申请日:2000-01-18

    CPC classification number: G01R31/3004 G01R31/3008

    Abstract: A CMOS integrated circuit is tested with the following steps: establishing a current threshold value (Ith), power the integrated circuit in static and idle conditions, measuring the current absorbed (IDDQ) by the integrated circuit and comparing this with the threshold value (Ith) and accepting or rejecting the integrated circuit if the comparison shows that the current absorbed measured (IDDQ) is respectively lower or higher than the threshold value (Ith). To improve discrimination between sound and faulty devices, the threshold value (Ith) is obtained from the following steps: forming two measurement transistors (Mn, Mp) in the integrated circuit, one n channel and the other p channel, biasing these in the cut-off zone and measuring their sub-threshold currents (Isubn, Isubp), calculating the sub-threshold currents by channel unit of area of the transistors of the integrated circuit using the sub-threshold currents measured (Isubn, Isubp) and the channel areas of the measurement transistors (Mn, Mp), obtaining the sum of the channel areas of the transistors that are cut off when the integrated circuit is idle in static conditions, calculating the current absorbed by the integrated circuit when idle in static conditions (IDDQ) using the result of the two operations described above and adding a pre-established current increase ΔI to the current absorbed (IDDQ) in order to obtain the threshold value (Ith).

    Abstract translation: CMOS集成电路通过以下步骤进行测试:建立电流阈值(Ith),在静态和空闲条件下为集成电路供电,测量集成电路的电流吸收(IDDQ),并将其与阈值(Ith)进行比较 )并且如果比较显示所测量的电流(IDDQ)分别低于或高于阈值(Ith),则接受或拒绝集成电路。 为了改善声音和故障装置之间的区别,从以下步骤获得阈值(Ith):在集成电路中形成两个测量晶体管(Mn,Mp),一个n沟道和另一个p沟道, 测量它们的亚阈值电流(Isubn,Isubp),使用测量的子阈值电流(Isubn,Isubp)和通道区域计算集成电路的晶体管面积的通道单位的子阈值电流 的测量晶体管(Mn,Mp),获得在静态条件下当集成电路处于空闲状态时被截止的晶体管的沟道面积之和,计算在静态条件(IDDQ)中空闲时由集成电路吸收的电流, 使用上述两种操作的结果,并将预先建立的电流增加量DELTA I添加到当前吸收(IDDQ)以获得阈值(Ith)。

    A method of testing an integrated circuit
    4.
    发明公开
    A method of testing an integrated circuit 有权
    VERFAHREN ZUR RUHESTROMBESTIMMUNG

    公开(公告)号:EP1085333A1

    公开(公告)日:2001-03-21

    申请号:EP99830581.7

    申请日:1999-09-14

    CPC classification number: G01R31/3008 G01R31/3004

    Abstract: A CMOS integrated circuit is tested by the following steps:

    supplying the integrated circuit in static conditions,
    biasing the p-type body regions (9) with a potential (VBBN) more negative than the negative pole (VSS) of the supply and the n-type body regions (12) with a potential (VBBP) more positive than the positive pole (VDD) of the supply,
    setting a current threshold value (Ith),
    measuring the current (IDDQ) absorbed,
    comparing the current (IDDQ) measured with the threshold current (Ith),
    accepting or rejecting the integrated circuit if the comparison shows that the current (IDDQ) measured is less than or is greater than the threshold value (Ith), respectively.

    Abstract translation: 通过以下步骤测试CMOS集成电路:将集成电路供给到静态条件下,用比电源的负极(VSS)更负的电位(VBBN)偏置p型体区域(9),并且n 具有比电源的正极(VDD)更正的电位(VBBP)的主体区域(12),设定电流阈值(Ith),测量吸收的电流(IDDQ),比较测量的电流(IDDQ) 如果比较显示测量的电流(IDDQ)分别小于或大于阈值(Ith),则阈值电流(Ith),接受或拒绝集成电路。

    METHOD FOR DETERMINING IDDQ
    5.
    发明授权
    METHOD FOR DETERMINING IDDQ 有权
    法闭路测定

    公开(公告)号:EP1085333B1

    公开(公告)日:2005-07-13

    申请号:EP99830581.7

    申请日:1999-09-14

    CPC classification number: G01R31/3008 G01R31/3004

    Abstract: A CMOS integrated circuit is tested by the following steps: supplying the integrated circuit in static conditions, biasing the p-type body regions (9) with a potential (VBBN) more negative than the negative pole (VSS) of the supply and the n-type body regions (12) with a potential (VBBP) more positive than the positive pole (VDD) of the supply, setting a current threshold value (Ith), measuring the current (IDDQ) absorbed, comparing the current (IDDQ) measured with the threshold current (Ith), accepting or rejecting the integrated circuit if the comparison shows that the current (IDDQ) measured is less than or is greater than the threshold value (Ith), respectively.

    A method and a circuit system for using equivalent integrated-circuit devices operating at different voltages
    6.
    发明公开
    A method and a circuit system for using equivalent integrated-circuit devices operating at different voltages 有权
    对于使用等效的集成电路元件的具有不同工作电压的方法和电路系统

    公开(公告)号:EP1152465A1

    公开(公告)日:2001-11-07

    申请号:EP00830323.2

    申请日:2000-05-04

    Abstract: The circuit system comprises an integrated circuit which is one of a family of equivalent integrated circuits that comprises a first-generation integrated circuit (IC1g') operating at the supply voltage of the circuit system (V) and at least one subsequent-generation integrated circuit (IC2g') having a portion (A') operating at a lower voltage. The first-generation integrated circuit (IC1g') has a direct electrical connection (SC) between one (VDD1g) of the supply terminals and another terminal (VDD2g). The subsequent-generation integrated circuit (IC2g') has a voltage reducer with regulator (RG) the output of which is connected to the said other terminal (VDD2g). A filter capacitor (C) is connected between the said other terminal (VDD2g) and one (VSS) of the supply terminals.

    Abstract translation: 该电路系统的集成电路包括所有这是一个家庭等效集成电路那样的中的一个包括第一代集成电路(IC1G“)在电路系统(V)和至少一个后续代集成电路的电源电压操作 (IC2g ')具有部分(A')在较低的电压下操作。 第一代集成电路(IC1G“)具有一个(VDD1g)之间的供给端子的直接电连接(SC)和另一个终端(VDD2g)。 后续代集成电路(IC2g“)具有与调节器(RG)的电压减速器的所有的输出被连接到另一端。所述(VDD2g)。 滤波电容器(C)被连接在电源端子的另一端与所述(VDD2g)和一个(VSS)之间。

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