公开(公告)号：EP1884786A1

公开(公告)日：2008-02-06

申请号：EP06425564.9

申请日：2006-08-04

Applicant: STMicroelectronics S.r.l.

Inventor： Danioni, Alberto ,  Invernizzi, Paolo

IPC: G01R19/22 ,  G01D3/02

CPC classification number: G01R19/22

Abstract: A signal-processing circuit (10) has a first and a second input (11a, 11b), which receive a first and a second differential signal (V P ,V M ), a third input (11c), which receives a common-mode signal (V CM ), the first and second differential signals (V P , V M ) having an equal and substantially opposite trend with respect to the common-mode signal (V CM ), and a first output (12a) supplying a first processed signal (V pp ), equivalent to the first differential signal (V P ) rectified with respect to the common-mode signal (V CM ), and satisfying throughout its course a first relation of comparison with the common-mode signal. The processing circuit (10) is provided with first formation means (14a, 16, 18) for formation of the first processed signal (V pp ), which operate on the basis of the first differential signal (V P ), and second formation means (14b, 16, 18) for formation of the first processed signal (V PP ), which operate on the basis of the second differential signal (V M ); the first and second formation means co-operate in the formation of the first processed signal.

Abstract translation: 信号处理电路（10）具有接收第一和第二差分信号（VP，VM）的第一和第二输入端（11a，11b），接收共模信号的第三输入端（11c） （V CM），相对于共模信号（V CM）具有相等且基本相反的趋势的第一和第二差分信号（VP，VM）以及提供第一处理信号（V pp），相当于相对于共模信号（V CM）整流的第一差分信号（VP），并且在整个过程中满足与共模信号的比较的第一关系。 处理电路（10）设置有用于形成基于第一差分信号（VP）工作的第一处理信号（V pp）的第一形成装置（14a，16,18）和第二形成装置 14b，16,18），用于形成基于第二差分信号（VM）工作的第一处理信号（V PP）; 第一和第二形成装置在形成第一处理信号时协同工作。