公开(公告)号：EP0877416A1

公开(公告)日：1998-11-11

申请号：EP97830212.3

申请日：1997-05-08

Applicant: STMicroelectronics S.r.l.

Inventor： Queirolo, Giuseppe ,  Ferroni, Giovanni

IPC: H01L21/20 ,  H01L21/3205 ,  H01L21/205 ,  H01L29/423 ,  H01L21/8247 ,  H01L29/92 ,  C23C16/24

CPC classification number: H01L28/82 ,  C23C16/24 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/3205

Abstract: The electrical performances of a dielectric film of capacitive coupling in an integrated structure are enhanced by forming the polycrystalline-metal electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. A process of forming a polycrystalline silicon film having exceptionally large grains of a size of the same order of magnitude of the dimensions of the patterned details is disclosed. These exceptionally large grains are obtained by preventing the formation of "precursor nuclei" of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

Abstract translation: 一体化结构中的电容耦合介电膜的电性能通过在耦合区域上形成与电介质膜基本上单晶的多晶金属导电层而增强，通常由图案化叠层的电介质层和导电层来限定。 公开了一种形成具有与图案化细节的尺寸相同数量级的尺寸异常大的晶粒的多晶硅膜的工艺。 这些特别大的晶粒是通过防止在与CVD电沉积的第一时刻显而易见地形成的电介质的沉积界面处形成后续晶粒形成和生长的“前体核”，并且通过依次将微晶足够低地生长 退火温度。