公开(公告)号：EP1715491B1

公开(公告)日：2009-12-16

申请号：EP06012616.6

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

公开(公告)号：EP1715491A3

公开(公告)日：2006-11-02

申请号：EP06012616.6

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

公开(公告)号：EP1715491A2

公开(公告)日：2006-10-25

申请号：EP06012616.6

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/04

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organised by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

Abstract translation: 本发明涉及一种调整半导体非易失性存储器中的擦除/编程电压的方法。 存储器由具有浮动栅极，控制栅极和漏极和源极端子的存储器单元的至少一个矩阵形成，并且由行（WL）和列（BL）中的字节组织，每个字节包括一组 具有通过字节开关类型的选择元件彼此并联连接到公共控制线（CG）的各个控制栅极的单元，并且每个单元通过位开关的选择元件连接到相应的控制列（BL） 类型。 有利地，为存储单元的编程电压提供双重调整，由此擦除阶段期间的编程电压可以比写入阶段期间的编程电压更高。 这通过在阱（13）内形成位开关元件（20）并直接在衬底中形成字节开关元件（21）来实现。

公开(公告)号：EP1079395A1

公开(公告)日：2001-02-28

申请号：EP99830478.6

申请日：1999-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico

IPC: G11C16/10

CPC classification number: G11C16/12

Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

Abstract translation: 该编程方法包括提供一个关断电压到所选择的单元的源极终端当写细胞。 所述关断电压是比最写入单元，即，最贫化单元的阈值电压的绝对值大振幅的正电压时，考虑到体效应。 例如，关断电压可以比最写入单元的阈值电压的绝对值大于1V。 有利的是，关断电压可以是5-6 V; 考虑到这个过程中，供应，和温度变化时，关断电压可以是7-8 V.的编程方法是有利地适用于EEPROM，带有分开的源极线的存储器装置，以便将关断电压只适用于被寻址的字节 或字节，或到包含寻址的字节的页面。

公开(公告)号：EP1047078A1

公开(公告)日：2000-10-25

申请号：EP99830235.0

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/30 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

Abstract: This invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows (WL) and columns (BL), each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line (CG) through a selection element of the byte switch type, and each cell being connected to a respective control column (BL) through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase.
This is achieved by providing respective adjusters (4,5) connected between a generator (7) of a program voltage (Vpp) and the cell matrix, or alternatively forming the bit switch element (20) inside a well (13) and the byte switch element (21) directly in the substrate.

Abstract translation: 一种非易失性存储器部分（1）包括包含如行字线（WL）和列作为位线（BL）的存储单元（2）的矩阵。 控制电路（3）包括一编程​​电压产生器（7）施加到矩阵行，第一调整器（4）调整到擦除电压的（VppE）上的电压（VST）的调整器（25）和第二（5 ）的写入电压（VppW）的。 在擦除阶段的编程电压设定为比在写作阶段更高。 因此独立claimsoft包括用于制造半导体非易失性存储器，包括形成阱内的位开关元件和在所述衬底的一个字节开关直接元件的过程。

公开(公告)号：EP1047078B1

公开(公告)日：2006-08-09

申请号：EP99830235.0

申请日：1999-04-21

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico ,  Zuliani, Paola

IPC: G11C16/30 ,  G11C16/12

CPC classification number: G11C16/12 ,  G11C16/0433 ,  G11C16/30

公开(公告)号：EP1227499B1

公开(公告)日：2006-05-10

申请号：EP01830039.2

申请日：2001-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: G11C16/08 ,  G11C7/18

CPC classification number: G11C16/08 ,  G11C7/18

公开(公告)号：EP1501130A1

公开(公告)日：2005-01-26

申请号：EP03425483.9

申请日：2003-07-21

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4238 ,  H01L21/28123

Abstract: A MOS semiconductor device comprising an active area (1) of semiconductor material is described. The active area (1) comprises a central part (10) and an edge (9) having a inclined surface with respect to the central part (10). The MOS device comprises a gate finger (2) placed over of the central part (10) of said active area and formed by an insulating material layer (11) adjacent to the active area (1) and a conductive material layer (20) over said insulating material layer (11). The MOS device comprises at least one first pair of prolongations (51, 61, 71, 72) of said gate finger (2) which derive from both its opposite sides (49) transversal to the formation of the channel under the gate finger (2) and which fmd in a direction substantially parallel to the formation of said channel. Said first pair of prolongations (51, 61, 71, 72) are placed over portions (48) of the edge (9) of the active area (1) which are parallel to the formation of said channel and over their adjacent portions (21) of the central part of the active area (1).

Abstract translation: 描述了包括半导体材料的有源区（1）的MOS半导体器件。 有源区域（1）包括中心部分（10）和相对于中心部分（10）具有倾斜表面的边缘（9）。 MOS器件包括放置在所述有源区的中心部分（10）上的栅极指（2），并由邻近有源区（1）的绝缘材料层（11）和导电材料层（20）形成 所述绝缘材料层（11）。 所述MOS器件包括所述栅极指（2）的至少一个第一对延伸部（51,61,71,72），所述第二对延伸部​​从所述栅极指（2）的下方形成沟槽的相对侧（49） ），并且在基本上平行于所述通道的形成的方向上fmd。 所述第一对延长部分（51,61,71,72）放置在有源区域（1）的边缘（9）的与所述通道的形成平行并且在其相邻部分（21）上的部分（48） ）活动区域（1）的中心部分。

公开(公告)号：EP1079395B1

公开(公告)日：2003-12-03

申请号：EP99830478.6

申请日：1999-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Gomiero, Enrico ,  Pio, Federico

IPC: G11C16/10

CPC classification number: G11C16/12

公开(公告)号：EP1227499A1

公开(公告)日：2002-07-31

申请号：EP01830039.2

申请日：2001-01-24

Applicant: STMicroelectronics S.r.l.

Inventor： Pio, Federico ,  Gomiero, Enrico

IPC: G11C16/08 ,  G11C7/18

CPC classification number: G11C16/08 ,  G11C7/18

Abstract: Non-volatile, electrically alterable semiconductor memory, comprising at least one two-dimensional array of memory cells with a plurality of rows (R0-R511) and a plurality of columns (C(0;0)-C(127;31)), column selection means (CADD,3;CADD,10,INT_CADD,3) for selecting columns among said plurality of columns, and a write circuit (7) for simultaneously writing a first number of memory cells. A plurality of doped semiconductor regions (40-4127) is provided, extending transversally to the rows and subdividing a set of memory cells of each row in a corresponding plurality of subsets of memory cells, each subset of memory cells including memory cells of the row formed in a respective doped semiconductor region distinct from the remaining doped semiconductor regions and defining an elementary memory block (P) that can be individually erased. The plurality of doped semiconductor regions define a plurality of column packets (C(0;0)-C(0;31),...,C(127;0)-C(127;31)) each one containing a second number of columns equal to or higher than said first number, memory cells (MC) belonging to columns of a same column packet being formed in a same doped semiconductor region distinct from the doped semiconductor regions in which memory cells belonging to columns of the other column packets are formed. The column selection means are such that within each column packet columns containing memory cells that can be written simultaneously by the write circuit are distributed among the columns of the column packet so as to be at the substantially maximum distance from each other allowable within the column packet.

Abstract translation: 包括具有多行（R0-R511）和多列（C（0; 0）-C（127; 31））的存储器单元的至少一个二维阵列的非易失性，电可更改的半导体存储器， 用于选择所述多个列中的列的列选择装置（CADD，3; CADD，10，INT_CADD，3）和用于同时写入第一数量的存储单元的写电路（7）。 提供了多个掺杂半导体区域（40-4127），其横向延伸到行并且在对应的多个存储器单元子集中细分每一行的一组存储器单元，每个存储单元子集包括行的存储单元 形成在与剩余的掺杂半导体区域不同的相应的掺杂半导体区域中，并且限定可被单独擦除的基本存储块（P）。 多个掺杂半导体区域限定多个列分组（C（0; 0）-C（0; 31），...，C（127; 0）-C（127; 31）） 等于或高于所述第一数量的列数，属于相同列分组的列的存储单元（MC）形成在与掺杂半导体区域不同的掺杂半导体区域中，其中属于另一列的列的存储单元 数据包被形成。 列选择装置使得在每列列中，包含可由写电路同时写入的存储单元的列被分布在列分组的列之间，以便在列分组内可允许的彼此基本上最大距离 。