公开(公告)号：EP3657676A1

公开(公告)日：2020-05-27

申请号：EP19211628.3

申请日：2019-11-26

Applicant: STMicroelectronics S.r.l.

Inventor： MUSSI, Giorgio ,  LANGFELDER, Giacomo ,  VALZASINA, Carlo ,  GATTERE, Gabriele

IPC: H03K5/13 ,  H03K5/156

Abstract: A clock generator (30) having a variable-modulus frequency divider (34), receiving a high-frequency clock signal (HFCK) and outputting a divided clock signal (DIV) having a frequency controlled by a modulus-control signal (MC) generated by a temperature-compensation circuit (36). A jitter filter (35) is coupled to the output of the variable-modulus frequency divider (34) and to the temperature-compensation circuit (36) and generates a compensated clock signal (OUT) having switching edges that are delayed, with respect to the divided clock signal (DIV), by a time correlated to a quantization-error signal.