公开(公告)号：EP1465365A1

公开(公告)日：2004-10-06

申请号：EP03425211.4

申请日：2003-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Macchetti, Marco ,  Fragneto, Paqualina ,  Bertoni, Guido Marco

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L2209/12

Abstract: A method for implementing one-to-one binary functions defined on the Galois field GF(2 8 ) is presented. This method is very useful for realizing fast and low-power hardware devices whichever the binary function is, and comprises the steps of

decoding an input byte generating at least one bit string that contains only one active bit;
logically combining the bits of the bit string according to the binary function for generating a 256-bit string representing a corresponding output byte;
encoding the 256-bit string in a byte, obtaining the output byte.

This method may be implemented by a fast and small area consuming hardware device for generating output bytes corresponding to respective input bytes according to an one-to-one binary function, comprising

a decoder of the input byte, generating at least one bit string that contains only one active bit;
an array of logic gates for input of the bit string, generating a 256-bit string by logically combining the bits of the input string according to the one-to-one binary function;
an encoder for input of the second 256-bit string, generating the output byte.

Abstract translation: 提出了一种用于实现在伽罗瓦域GF（2,8）上定义的一对一二进制函数的方法。 该方法对于实现二进制功能的快速和低功率硬件设备非常有用，并且包括对产生至少一个仅包含一个活动位的位串的输入字节进行解码的步骤; 根据用于产生表示相应输出字节的256位串的二进制功能逻辑组合位串的位; 以字节编码256位字符串，获取输出字节。 该方法可以由快速且小的面积消耗的硬件设备来实现，用于根据一对一二进制功能产生对应于相应输入字节的输出字节，包括输入字节的解码器，产生至少一个 只包含一个活动位的位串; 用于输入位串的逻辑门阵列，通过根据一对一二进制函数逻辑组合输入串的位来产生256位串; 用于输入第二256位串的编码器，产生输出字节。