公开(公告)号：EP1137162A1

公开(公告)日：2001-09-26

申请号：EP00830225.9

申请日：2000-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Palestra, Marco

IPC: H02M7/5387

CPC classification number: H02M7/53873

Abstract: A feedback control circuit of the current in a load constituted by a winding in series to a current sensing resistor, coupled to a full-bridge output stage, an amplifier (SENSE_AMPL) coupled to the terminals of the sensing resistor, a controller fed with the output of the amplifier and with a voltage reference (V IN ) and producing a correction signal, has a PWM converter for generating a pair of control signals (I N +, I N -) that comprises an up/down counter producing a count value and a logic circuitry that produces the complement to two of the correction signal. A pair of registers first (D_I N +) and second (D_I N -) are coupled to the outputs of the controller and of the logic circuitry. A first comparator (COMP_1) coupled to the outputs of the counter and of the first register (D_I N +) produces the first control signal (I N +) if the count signal exceeds the value stored in the first register (D_I N +) and a second comparator (COMP_2) coupled to the counter and to the second register (D_I N -), produces the second control signal (I N -) if the count signal overcomes the value stored in the second register (D_I N -).

Abstract translation: 负载中的电流的反馈控制电路由串联连接到电流检测电阻器的绕组构成，耦合到全桥输出级，耦合到感测电阻器的端子的放大器（SENSE_AMPL），馈送有 具有用于产生一对控制信号（IN +，IN-）的PWM转换器，所述PWM转换器包括放大器的输出和参考电压（VIN）并产生校正信号，所述控制信号包括产生计数值的上/下计数器和逻辑电路 其产生对两个校正信号的补码。 一对寄存器（D_IN +）和第二（D_IN-）被耦合到控制器和逻辑电路的输出。 如果计数信号超过存储在第一寄存器（D_IN +）中的值和第二比较器（COMP_2），则耦合到计数器和第一寄存器（D_IN +）的输出的第一比较器（COMP_1）产生第一控制信号 ），如果计数信号克服存储在第二寄存器（D_IN-）中的值，则产生第二控制信号（IN-）到计数器和第二寄存器（D_IN-）。

公开(公告)号：EP1137162B1

公开(公告)日：2005-02-16

申请号：EP00830225.9

申请日：2000-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Palestra, Marco

IPC: H02M7/5387

CPC classification number: H02M7/53873